P

Inventor

GAERTNER UTE

DE53 patents
⚠️ This page may combine multiple inventors who share the name “GAERTNER UTE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

41 patents
US5761734AJun 2, 1998

Token-based serialisation of instructions in a multiprocessor system

IBM272 citations98
US6418522B1Jul 9, 2002

Translation lookaside buffer for virtual memory systems

IBM81 citations97
US6996698B2Feb 7, 2006

Blocking processing restrictions based on addresses

IBM51 citations96
US9432183B1Aug 30, 2016

Encrypted data exchange between computer systems

IBM27 citations94
US9697135B2Jul 4, 2017

Suppressing virtual address translation utilizing bits and instruction tagging

IBM17 citations92
US9330018B2May 3, 2016

Suppressing virtual address translation utilizing bits and instruction tagging

IBM22 citations92
US9330017B2May 3, 2016

Suppressing virtual address translation utilizing bits and instruction tagging

IBM19 citations92
US9092382B2Jul 28, 2015

Reducing microprocessor performance loss due to translation table coherency in a multi-processor system

IBM22 citations92
US9069715B2Jun 30, 2015

Reducing microprocessor performance loss due to translation table coherency in a multi-processor system

IBM17 citations92
US7530067B2May 5, 2009

Filtering processor requests based on identifiers

IBM17 citations92
US7020761B2Mar 28, 2006

Blocking processing restrictions based on page indices

IBM26 citations92
US6108771AAug 22, 2000

Register renaming with a pool of physical registers

IBM26 citations92
US5996063ANov 30, 1999

Management of both renamed and architected registers in a superscalar computer system

IBM28 citations92
US6237076B1May 22, 2001

Method for register renaming by copying a 32 bits instruction directly or indirectly to a 64 bits instruction

IBM22 citations91
US9596076B1Mar 14, 2017

Encrypted data exchange between computer systems

IBM7 citations84
US6766434B2Jul 20, 2004

Method for sharing a translation lookaside buffer between CPUs

IBM18 citations84
US10102151B2Oct 16, 2018

Protecting a memory from unauthorized access

IBM4 citations73
US10102152B2Oct 16, 2018

Protecting a memory from unauthorized access

IBM2 citations73
US10025608B2Jul 17, 2018

Quiesce handling in multithreaded environments

IBM4 citations73
US9798678B2Oct 24, 2017

Protecting storage from unauthorized access

IBM2 citations73
US9779032B2Oct 3, 2017

Protecting storage from unauthorized access

IBM2 citations73
US9372805B2Jun 21, 2016

Operating on translation look-aside buffers in a multiprocessor environment

IBM4 citations72
US11036647B2Jun 15, 2021

Suspending translation look-aside buffer purge execution in a multi-processor environment

IBM0 citations62
US10929312B2Feb 23, 2021

Zone-SDID mapping scheme for TLB purges

IBM0 citations62
US7401185B2Jul 15, 2008

Buffered indexing to manage hierarchical tables

IBM2 citations61
US5978957ANov 2, 1999

Very fast pipelined shifter element with parity prediction

IBM3 citations61
US10353828B2Jul 16, 2019

Zone-SDID mapping scheme for TLB purges

IBM0 citations52
US10353827B2Jul 16, 2019

Zone-SDID mapping scheme for TLB purges

IBM0 citations52
US10176002B2Jan 8, 2019

Quiesce handling in multithreaded environments

IBM0 citations52
US10013279B2Jul 3, 2018

Processing interrupt requests

IBM0 citations52
US10002022B2Jun 19, 2018

Processing interrupt requests

IBM0 citations52
US9772954B2Sep 26, 2017

Protecting contents of storage

IBM0 citations52
US9715462B2Jul 25, 2017

Protecting contents of storage

IBM0 citations52
US9678830B2Jun 13, 2017

Recovery improvement for quiesced systems

IBM0 citations52
US9665424B2May 30, 2017

Recovery improvement for quiesced systems

IBM0 citations52
US9274957B2Mar 1, 2016

Monitoring a value in storage without repeated storage access

IBM0 citations52
US10698835B2Jun 30, 2020

Suspending translation look-aside buffer purge execution in a multi-processor environment

IBM0 citations51
US10353825B2Jul 16, 2019

Suspending translation look-aside buffer purge execution in a multi-processor environment

IBM0 citations51
US10248575B2Apr 2, 2019

Suspending translation look-aside buffer purge execution in a multi-processor environment

IBM0 citations51
US12013791B2Jun 18, 2024

Reset dynamic address translation protection instruction

IBM0 citations49
US11593275B2Feb 28, 2023

Operating system deactivation of storage block write protection absent quiescing of processors

IBM0 citations49

HELLER LISA C

4 patents

FERTIG MATTHIAS

1 patent

DEUTSCHLE JOERG

1 patent

GAERTNER UTE

1 patent

ALEXANDER KHARY J

1 patent

SLEGEL TIMOTHY J

1 patent

Showing the top 50 of 53 patents by PatentIndex Score.