Inventor

LIOU SHIANN-MING

US71 patents

⚠️ This page may combine multiple inventors who share the name “LIOU SHIANN-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIOU SHIANN-MING

MARVELL INT LTD

Integrated circuit devices with ESD and I/O protection

Semiconductor package

Semiconductor device power distribution system and method

Semiconductor die having lead wires formed over a circuit in a shielded area

Semiconductor package

Integrated circuit packaging configurations

Leadless multi-chip module structure

Pre-formed conductive bumps on bonding pads

Thermal solution for drive systems such as hard disk drives and digital versatile discs

Thermal solution for drive systems such as hard disk drives and digital versatile discs

Method of fabricating a device with ESD and I/O protection

Pillar structure on bump pad

Semiconductor device power distribution system and method

Leadframe with improved half-etch layout to reduce defects caused during singulation

Leadless multi-chip module structure

Method for forming one or more vias through a semiconductor substrate and forming a redistribution layer on the semiconductor substrate

Etched hybrid die package

Pillar structure on bump pad

Die-to-die wire-bonding

Drop-in heat sink and exposed die-back for molded flip die package

LIOU SHIANN-MING

Integrated circuit packaging configurations

Semiconductor device having lead wires connecting bonding pads formed on opposite sides of a core region forming a shield area

Semiconductor package

Semiconductor dice having a shielded area created under bond wires connecting pairs of bonding pads

Pre-formed conductive bumps on bonding pads

Through via semiconductor die with backside redistribution layer

Single layer BGA substrate process

MARVELL WORLD TRADE LTD

Thermal enhanced package

Package-on-package structures

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

Semiconductor packaging with internal wiring bus

Package assembly having a semiconductor substrate

Dual row quad flat no-lead semiconductor package

Ball grid array package substrate with through holes and method of forming same

NAT SEMICONDUCTOR CORP

Process for attaching a lead frame to a heat sink using a glob-top encapsulation

Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created

IC having heat spreader attached by glob-topping

Method and structure for forming vertical semiconductor interconnection

KAO HUAHUNG

Package-on-package structures

Stack die structure for stress reduction and facilitation of electromagnetic shielding

Interconnect layouts for electronic assemblies

INNOGRIT TECHNOLOGIES CO LTD

Removable non-volatile storage card

Ground reference shape for high speed interconnect

Semiconductor die with hybrid wire bond pads

WU ALBERT

Semiconductor package with a semiconductor die embedded within substrates

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

LIU CHENGLIN

Etched hybrid die package

CHEN CHENDER

Placing heat sink into packaging by strip formation assembly

SUTARDJA SEHAT

Pad configurations for an electronic package assembly

MARVELL INT TECHNOLOGY LTD

Thermal enhanced package