Inventor

LIN CHIA-PIN

TW95 patents

⚠️ This page may combine multiple inventors who share the name “LIN CHIA-PIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN CHIA-PIN

TAIWAN SEMICONDUCTOR MFG CO LTD

Integrated circuit structure with backside dielectric layer having air gap

Inner spacer liner

Inner spacer features for multi-gate transistors

Semiconductor device with backside contact and methods of forming such

Transistor source/drain regions and methods of forming the same

Semiconductor device active region profile and method of forming the same

Inner spacer liner

Structure and formation method of semiconductor device with backside contact

Nano-FET semiconductor device and method of forming

Semiconductor structure with gate-all-around devices and stacked FinFET devices

Epitaxial source/drain feature with enlarged lower section interfacing with backside via

Semiconductor device active region profile and method of forming the same

Lightly-doped channel extensions

Integrated circuit structure with backside dielectric layer having air gap

Semiconductor devices including backside vias and methods of forming the same

Method and structure for air gap inner spacer in gate-all-around devices

Method of making a finFET, and finFET formed by the method

Method and structure for air gap inner spacer in gate-all-around devices

Spacer features for nanosheet-based devices

Semiconductor device with leakage current suppression and method for forming the same

Multi-gate semiconductor device with inner spacer and fabrication method thereof

Dual epitaxial process for a finFET device

Gate-all-around transistor having inner space lined by a semiconductor liner and method of forming the same

Semiconductor device active region profile and method of forming the same

Epitaxial source/drain feature with enlarged lower section interfacing with backside via

Semiconductor device structure with backside contact

Semiconductor structure with gate-all-around devices and stacked FinFET devices

Method of manufacturing a semiconductor device and a semiconductor device

Nano-FET semiconductor device and method of forming

Semiconductor device with leakage current suppression and method for forming the same

Inner spacer features for multi-gate transistors

Asymmetric source/drain for backside source contact

Integrated circuit structure with backside dielectric layer having air gap

Semiconductor devices including backside vias and methods of forming the same

Asymmetric source/drain for backside source contact

Devices with improved operational current and reduced leakage current

Methods for forming source/drain features

TAIWAN SEMICONDUCTOR MFG

Lower parasitic capacitance FinFET

Method of making lower parasitic capacitance FinFET

Gate structures

Hybrid gate process for fabricating FinFET device

Integrated method for forming high-k metal gate FinFET devices

Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure

TSENG CHIH-HUNG

Transistor having notched fin structure and method of making the same

LIM PENG-SOON

Method of fabricating gate structures

HUANG YU-LIEN

Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure

GAN TIAN-CHOY

Hybrid gate process for fabricating finfet device

CHEN HUNG-KAI

Dual epitaxial process for a finFET device

LIN CHIA-PIN

Method of making a finFET, and finFET formed by the method

TRANSCEND INFORMATION INC

Charge/discharge control circuit and charge/discharge method thereof