P

Inventor

DAMLE PRASHANT S

US27 patents
⚠️ This page may combine multiple inventors who share the name “DAMLE PRASHANT S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

23 patents
US9824767B1Nov 21, 2017

Methods and apparatus to reduce threshold voltage drift

INTEL CORP25 citations91
US9613691B2Apr 4, 2017

Apparatus and method for drift cancellation in a memory

INTEL CORP20 citations91
US10324793B2Jun 18, 2019

Reduced uncorrectable memory errors

INTEL CORP4 citations84
US9721657B1Aug 1, 2017

Managing threshold voltage shift in nonvolatile memory

INTEL CORP6 citations84
US9202547B2Dec 1, 2015

Managing disturbance induced errors

INTEL CORP8 citations84
US9136873B2Sep 15, 2015

Reduced uncorrectable memory errors

INTEL CORP8 citations84
US9032137B2May 12, 2015

Flexible wear management for non-volatile memory

INTEL CORP11 citations83
US9934859B1Apr 3, 2018

Determining demarcation voltage via timestamps

INTEL CORP9 citations81
US9384801B2Jul 5, 2016

Threshold voltage expansion

INTEL CORP8 citations81
US9286975B2Mar 15, 2016

Mitigating read disturb in a cross-point memory

INTEL CORP18 citations80
US10777271B2Sep 15, 2020

Method and apparatus for adjusting demarcation voltages based on cycle count metrics

INTEL CORP2 citations73
US10679698B2Jun 9, 2020

Memory preset adjustment based on adaptive calibration

INTEL CORP5 citations73
US10331345B2Jun 25, 2019

Method and apparatus for reducing silent data errors in non-volatile memory systems

INTEL CORP4 citations73
US9934088B2Apr 3, 2018

Reduced uncorrectable memory errors

INTEL CORP2 citations73
US9792963B2Oct 17, 2017

Managing disturbance induced errors

INTEL CORP2 citations73
US9619324B2Apr 11, 2017

Error correction in non—volatile memory

INTEL CORP6 citations73
US10936418B2Mar 2, 2021

Reduced uncorrectable memory errors

INTEL CORP0 citations62
US10310989B2Jun 4, 2019

Time tracking with patrol scrub

INTEL CORP1 citations60
US11404105B2Aug 2, 2022

Write disturb refresh rate reduction using write history buffer

INTEL CORP0 citations56
US10153015B2Dec 11, 2018

Managing disturbance induced errors

INTEL CORP0 citations52
US10056139B2Aug 21, 2018

Managing threshold voltage shift in nonvolatile memory

INTEL CORP1 citations52
US12230346B2Feb 18, 2025

Cross-point memory read technique to mitigate drift errors

INTEL CORP0 citations51
US9501405B2Nov 22, 2016

Flexible wear management for non-volatile memory

INTEL CORP0 citations51

DAMLE PRASHANT S

2 patents

MICRON TECHNOLOGY INC

1 patent

RIVERS DOYLE

1 patent