Inventor

RAMACHANDRAN RAVIKUMAR

US113 patents

⚠️ This page may combine multiple inventors who share the name “RAMACHANDRAN RAVIKUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMACHANDRAN RAVIKUMAR

IBM

Method for forming merged contact for semiconductor device

Contact first replacement metal gate

Strained finFET with an electrically isolated channel

Semiconductor device having dual metal gates and method of manufacture

Deep trench capacitor with buried plate electrode and isolation collar

Uniform finFET gate height

Slurry-less chemical-mechanical polishing

Method to minimize watermarks on silicon substrates

Manufacturing of cavity fuses on gate conductor level

Etching composition and use thereof

Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

Multi-composition gate dielectric field effect transistors

Fin field effect transistors having heteroepitaxial channels

Strained finFET with an electrically isolated channel

FinFET having suppressed leakage current

Replacement metal gate structures providing independent control on work function and gate leakage current

Uniform finFET gate height

FinFET device formation

Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel

Nitrogen based plasma process for metal gate MOS device

Multiple thickness gate dielectrics for replacement gate field effect transistors

Method of forming gate stack and structure thereof

Dual metal and dual dielectric integration for metal high-k FETs

Field effect device including inverted V shaped channel region and method for fabrication thereof

Vertical hard mask

Stacked FET SRAM

Method for fabricating a trench having a buried dielectric collar

Gate metal recess for oxidation protection and parasitic capacitance reduction

INFINEON TECHNOLOGIES AG

Method of fabricating a bottle trench and a bottle trench capacitor

MRAM MTJ stack to conductive line alignment method

Clean method for recessed conductive barriers

Ceria slurry solution for improved defect control of silicon dioxide chemical-mechanical polishing

Dual gate oxide process without critical resist and without N2 implant

Compositions for and method of reducing/eliminating scratches and defects in silicon dioxide during CMP process

Low temperature sidewall oxidation of W/WN/poly-gatestack

Increased polish removal rate of dielectric layers using fixed abrasive pads

SIEMENS AG

Apparatus and method for improved washing and drying of semiconductor wafers

Apparatus and method for improved washing and drying of semiconductor wafers

Removal of post-RIE polymer on Al/Cu metal line

Composition and method for reducing dishing in patterned metal during CMP process

Method of reducing the formation of watermarks on semiconductor wafers

RAMACHANDRAN RAVIKUMAR

Self-aligned contact for replacement gate devices

Self-aligned contacts for high k/metal gate process flow

KWON UNOH

Replacement metal gate structures for effective work function control

Replacement metal gate structures providing independent control on work function and gate leakage current

GLOBALFOUNDRIES INC

Forming fins of different semiconductor materials on the same substrate

Self-aligned contact for replacement gate devices

UTOMO HENRY K

Planar silicide semiconductor structure

Structure and method for replacement metal gate field effect transistors

INFINEON TECHNOLOGIES CORP

Vertical semiconductor devices