Inventor

SHANG HUILING

US41 patents

⚠️ This page may combine multiple inventors who share the name “SHANG HUILING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHANG HUILING

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device structure with metal gate stack

Semiconductor device with air spacer and stress liner

Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

Devices with strained isolation features

Semiconductor device with S/D bottom isolation and methods of forming the same

Semiconductor device with S/D bottom isolation and methods of forming the same

Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

Semiconductor device structure with metal gate stack

Semiconductor device having contact feature and method of fabricating the same

Devices with strained isolation features

Integrated circuits with channel-strain liner

Semiconductor device having contact feature and method of fabricating the same

Integrated circuits with channel-strain liner

Gate cut dielectric feature and method of forming the same

Structure and formation method of semiconductor device with metal gate stack

Multi-gate device including semiconductor fin between dielectric fins and method of fabrication thereof

IBM

Integration of strained Ge into advanced CMOS technology

Strained finFET with an electrically isolated channel

Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby

Strained finFET with an electrically isolated channel

Method of forming a semiconductor structure using a non-oxygen chalcogen passivation treatment

Integration of strained Ge into advanced CMOS technology

Silicon-germanium fins and silicon fins on a bulk substrate

Thin germanium oxynitride gate dielectric for germanium-based devices

Process for passivating the semiconductor-dielectric interface of a MOS device and MOS device formed thereby

MOS device having a passivated semiconductor-dielectric interface

Semiconductor fin isolation by a well trapping fin portion

Integration of strained Ge into advanced CMOS technology

Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby

High threshold voltage NMOS transistors for low power IC technology

Semiconductor fin isolation by a well trapping fin portion

Semiconductor fin isolation by a well trapping fin portion

CHOU ANTHONY I

Bulk substrate FET integrated on CMOS SOI

Bulk substrate FET integrated on CMOS SOI

GLOBALFOUNDRIES INC

Forming fins of different semiconductor materials on the same substrate

ANDO TAKASHI

Source-drain extension formation in replacement metal gate transistor device

CHANG LELAND

Contact scheme for FINFET structures with multiple FINs

SHANG HUILING

Method of forming a shallow trench isolation embedded polysilicon resistor

CABRAL JR CYRIL

Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby

CHAN VICTOR W C

High threshold voltage NMOS transistors for low power IC technology