Inventor
HARIKUMAR AJAY
US10 patents
⚠️ This page may combine multiple inventors who share the name “HARIKUMAR AJAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
7 patentsUS7987352B2Jul 26, 2011
Booting with sub socket partitioning
INTEL CORP21 citations90
US10984096B2Apr 20, 2021
Systems, methods, and apparatus for detecting control flow attacks
INTEL CORP5 citations71
US11126721B2Sep 21, 2021
Methods, systems and apparatus to detect polymorphic malware
INTEL CORP0 citations60
US8850081B2Sep 30, 2014
Method, system and apparatus for handling events for partitions in a socket with sub-socket partitioning
INTEL CORP3 citations56
US8370508B2Feb 5, 2013
Method, system and apparatus for main memory access subsystem usage to different partitions in a socket with sub-socket partitioning
INTEL CORP1 citations49
US10395033B2Aug 27, 2019
System, apparatus and method for performing on-demand binary analysis for detecting code reuse attacks
INTEL CORP0 citations39
US10789056B2Sep 29, 2020
Technologies for scalable translation caching for binary translation systems
INTEL CORP0 citations37
HARIKUMAR AJAY
3 patentsUS8635380B2Jan 21, 2014
Method, system and apparatus for handling events for partitions in a socket with sub-socket partitioning
HARIKUMAR AJAY5 citations80
US8296522B2Oct 23, 2012
Method, apparatus, and system for shared cache usage to different partitions in a socket with sub-socket partitioning
HARIKUMAR AJAY3 citations58
US8151081B2Apr 3, 2012
Method, system and apparatus for memory address mapping for sub-socket partitioning
HARIKUMAR AJAY2 citations58