Inventor

HU XINDE

US45 patents

⚠️ This page may combine multiple inventors who share the name “HU XINDE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HU XINDE

SANDISK TECHNOLOGIES INC

Adaptive redundancy in three dimensional memory

Parity scheme for a data storage device

Structure variation detection for a memory having a three-dimensional memory configuration

Data reprogramming for a data storage device

System and method of separating read intensive addresses from non-read intensive addresses

On-chip copying of data between NAND flash memory and ReRAM of a memory die

Counter for write operations at a data storage device

Memory device with resistive random access memory (ReRAM)

Data encoding techniques for a device

Data retention in a memory block based on local heating

Parity scheme for a data storage device

Memory access techniques for a memory having a three-dimensional memory configuration

Metalblock relinking to physical blocks of semiconductor memory in adaptive wear leveling based on health

Tag-based wear leveling for a data storage device

Error correcting code techniques for a memory having a three-dimensional memory configuration

Method and device for write abort protection

Method and system for adaptively assigning logical block address read counters using a tree structure

System and method for utilizing history information in a memory device

WESTERN DIGITAL TECH INC

Non-volatile memory sub-block erasure disturb management scheme

Selecting reversible resistance memory cells based on initial resistance switching

Wear leveling methods for zoned namespace solid state drive

Flash memory polling

Bounded latency and command non service methods and apparatus

Bounded latency and command non service methods and apparatus

Storing log and user data in SSD with independent plane operations

HU XINDE

Asymmetric log-likelihood ratio for MLC flash channel

Trellis-coded modulation in a multi-level cell flash memory device

Interlaced iterative system design for 1K-byte block with 512-byte LDPC codewords

Low density parity check code decoding system and method

System and method for determining data dependent noise calculation for a flash channel

STEC INC

Dynamic LDPC code rate solution

Reduced complexity non-binary LDPC decoding algorithm

Read level adjustment using soft information

Soft information module

HGST TECH SANTA ANA INC

Soft information module

Reduced complexity non-binary LDPC decoding algorithm

Soft information module

SANDISK TECHNOLOGIES LLC

Error correcting code adjustment for a data storage device

Non-volatile memory with dynamic repurpose of word line

HGST Netherlands BV

Asymmetric log-likelihood ratio for flash channel

Asymmetric log-likelihood ratio for flash channel

WEATHERS ANTHONY D

Optimal programming levels for LDPC

HGST TECHNOLOGIES SANTA ANA INC

Reduced complexity non-binary LDPC decoding algorithm

SANDISK TECHNOLOGY INC

Method and device for write abort protection

ST MICROELECTRONICS INC

Channel constrained code aware interleaver