Inventor

NISHIKAWA HIROO

JP3 patents

⚠️ This page may combine multiple inventors who share the name “NISHIKAWA HIROO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

2 patents

US7392270B2Jun 24, 2008

Apparatus and method for reducing the latency of sum-addressed shifters

IBM7 citations72

US7469265B2Dec 23, 2008

Methods and apparatus for performing multi-value range checks

IBM0 citations50

DHONG SANG HOO

1 patent

US8166085B2Apr 24, 2012

Reducing the latency of sum-addressed shifters

DHONG SANG HOO1 citations50