Inventor
WONG KEITH KWONG HON
US207 patents
⚠️ This page may combine multiple inventors who share the name “WONG KEITH KWONG HON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
23 patentsUS7557424B2Jul 7, 2009
Reversible electric fuse and antifuse structures for semiconductor devices
IBM75 citations98
US7531407B2May 12, 2009
Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same
IBM61 citations98
US7394332B2Jul 1, 2008
Micro-cavity MEMS device and method of fabricating same
IBM45 citations94
US8009453B2Aug 30, 2011
High density planar magnetic domain wall memory apparatus
IBM15 citations93
US7973409B2Jul 5, 2011
Hybrid interconnect structure for performance improvement and reliability enhancement
IBM24 citations93
US7838873B2Nov 23, 2010
Structure for stochastic integrated circuit personalization
IBM17 citations93
US7838908B2Nov 23, 2010
Semiconductor device having dual metal gates and method of manufacture
IBM28 citations93
US7598545B2Oct 6, 2009
Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices
IBM20 citations93
US7514271B2Apr 7, 2009
Method of forming high density planar magnetic domain wall memory
IBM36 citations93
US6700203B1Mar 2, 2004
Semiconductor structure having in-situ formed unit resistors
IBM28 citations93
US7851321B2Dec 14, 2010
Semiconductor integrated circuit devices having high-Q wafer back-side capacitors
IBM16 citations92
US7750418B2Jul 6, 2010
Introduction of metal impurity to change workfunction of conductive electrodes
IBM18 citations92
US7473979B2Jan 6, 2009
Semiconductor integrated circuit devices having high-Q wafer back-side capacitors
IBM18 citations92
US7365001B2Apr 29, 2008
Interconnect structures and methods of making thereof
IBM35 citations92
US7276796B1Oct 2, 2007
Formation of oxidation-resistant seed layer for interconnect applications
IBM17 citations92
US9171954B2Oct 27, 2015
FinFET structure and method to adjust threshold voltage in a FinFET structure
IBM9 citations84
US9099493B2Aug 4, 2015
Semiconductor device with raised source/drain and replacement metal gate
IBM9 citations84
US8853788B2Oct 7, 2014
Replacement gate electrode with planar work function material layers
IBM6 citations84
US8796854B2Aug 5, 2014
Hybrid interconnect structure for performance improvement and reliability enhancement
IBM6 citations84
US8741700B1Jun 3, 2014
Non-volatile graphene nanomechanical switch
IBM8 citations84
US8735947B1May 27, 2014
Non-volatile graphene nanomechanical switch
IBM12 citations84
US8023305B2Sep 20, 2011
High density planar magnetic domain wall memory apparatus
IBM11 citations84
US7999323B2Aug 16, 2011
Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices
IBM7 citations84
GUO DECHAO
10 patentsUS9142660B2Sep 22, 2015
Method to fabricate a vertical transistor having an asymmetric gate with two conductive layers having different work functions
GUO DECHAO17 citations93
US8084346B1Dec 27, 2011
Replacement metal gate method
GUO DECHAO26 citations93
US8866214B2Oct 21, 2014
Vertical transistor having an asymmetric gate
GUO DECHAO13 citations84
US8686514B2Apr 1, 2014
Multiple threshold voltages in field effect transistor devices
GUO DECHAO9 citations84
US8569135B2Oct 29, 2013
Replacement gate electrode with planar work function material layers
GUO DECHAO10 citations84
US8519454B2Aug 27, 2013
Structure and process for metal fill in replacement metal gate integration
GUO DECHAO9 citations84
US8513081B2Aug 20, 2013
Carbon implant for workfunction adjustment in replacement gate transistor
GUO DECHAO12 citations84
US8455365B2Jun 4, 2013
Self-aligned carbon electronics with embedded gate electrode
GUO DECHAO9 citations84
US8288217B2Oct 16, 2012
Stressor in planar field effect transistor device
GUO DECHAO6 citations84
US8268689B2Sep 18, 2012
Multiple threshold voltages in field effect transistor devices
GUO DECHAO8 citations84
CHENG KANGGUO
4 patentsUS8546209B1Oct 1, 2013
Replacement metal gate processing with reduced interlevel dielectric layer etch rate
CHENG KANGGUO35 citations94
US8530971B2Sep 10, 2013
Borderless contacts for semiconductor devices
CHENG KANGGUO14 citations93
US8450178B2May 28, 2013
Borderless contacts for semiconductor devices
CHENG KANGGUO10 citations84
US8324058B2Dec 4, 2012
Contacts for FET devices
CHENG KANGGUO9 citations84
GLOBALFOUNDRIES INC
4 patentsUS9343372B1May 17, 2016
Metal stack for reduced gate resistance
GLOBALFOUNDRIES INC23 citations92
US9905476B2Feb 27, 2018
Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
GLOBALFOUNDRIES INC9 citations84
US9553092B2Jan 24, 2017
Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
GLOBALFOUNDRIES INC15 citations84
US9505611B1Nov 29, 2016
Integration of electromechanical and CMOS devices in front-end-of-line using replacement metal gate process flow
GLOBALFOUNDRIES INC18 citations84
CAO QING
2 patentsYANG CHIH-CHAO
2 patentsINFINEON TECHNOLOGIES AG
1 patentWONG KEITH KWONG HON
1 patentLI ZHENGWEN
1 patentCHAN KEVIN K
1 patentANDO TAKASHI
1 patentShowing the top 50 of 207 patents by PatentIndex Score.