Inventor
MCCALL JAMES A
US81 patents
⚠️ This page may combine multiple inventors who share the name “MCCALL JAMES A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
45 patentsUS6820163B1Nov 16, 2004
Buffering data transfer between a chipset and memory modules
INTEL CORP118 citations98
US6771515B2Aug 3, 2004
Systems having modules with on die terminations
INTEL CORP29 citations92
US6747483B2Jun 8, 2004
Differential memory interface system
INTEL CORP29 citations92
US6674648B2Jan 6, 2004
Termination cards and systems therefore
INTEL CORP29 citations92
US6366466B1Apr 2, 2002
Multi-layer printed circuit board with signal traces of varying width
INTEL CORP50 citations92
US9934842B2Apr 3, 2018
Multiple rank high bandwidth memory
INTEL CORP15 citations91
US7772708B2Aug 10, 2010
Stacking integrated circuit dies
INTEL CORP21 citations88
US7542322B2Jun 2, 2009
Buffered continuous multi-drop clock ring
INTEL CORP33 citations87
US6700457B2Mar 2, 2004
Impedance compensation for circuit board breakout region
INTEL CORP20 citations86
US10146711B2Dec 4, 2018
Techniques to access or operate a dual in-line memory module via multiple data channels
INTEL CORP14 citations84
US10031868B2Jul 24, 2018
Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines
INTEL CORP4 citations84
US9665527B2May 30, 2017
Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines
INTEL CORP4 citations84
US9218575B2Dec 22, 2015
Periodic training for unmatched signal receiver
INTEL CORP14 citations84
US7676917B2Mar 16, 2010
Method of manufacturing a circuit board
INTEL CORP9 citations84
US7246022B2Jul 17, 2007
Initiation of differential link retraining upon temperature excursion
INTEL CORP11 citations83
US6711027B2Mar 23, 2004
Modules having paths of different impedances
INTEL CORP14 citations82
US7194572B2Mar 20, 2007
Memory system and method to reduce reflection and signal degradation
INTEL CORP9 citations74
US7133962B2Nov 7, 2006
Circulator chain memory command and address bus topology
INTEL CORP7 citations74
US6724082B2Apr 20, 2004
Systems having modules with selectable on die terminations
INTEL CORP8 citations74
US6711640B1Mar 23, 2004
Split delay transmission line
INTEL CORP7 citations74
US6708243B1Mar 16, 2004
Computer assembly with stub traces coupled to vias to add capacitance at the vias
INTEL CORP9 citations74
US6686762B2Feb 3, 2004
Memory module using DRAM package to match channel impedance
INTEL CORP8 citations74
US6597202B1Jul 22, 2003
Systems with skew control between clock and data signals
INTEL CORP9 citations74
US6515555B2Feb 4, 2003
Memory module with parallel stub traces
INTEL CORP8 citations74
US11056179B2Jul 6, 2021
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
INTEL CORP1 citations73
US10884958B2Jan 5, 2021
DIMM for a high bandwidth memory channel
INTEL CORP2 citations73
US10592445B2Mar 17, 2020
Techniques to access or operate a dual in-line memory module via multiple data channels
INTEL CORP2 citations73
US10437746B2Oct 8, 2019
Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines
INTEL CORP2 citations73
US10025685B2Jul 17, 2018
Impedance compensation based on detecting sensor data
INTEL CORP2 citations73
US9786353B2Oct 10, 2017
Reconfigurable clocking architecture
INTEL CORP4 citations73
US9595963B2Mar 14, 2017
Method and apparatus for dynamic memory termination
INTEL CORP3 citations73
US9552164B2Jan 24, 2017
Apparatus, method and system for determining reference voltages for a memory
INTEL CORP4 citations73
US7459200B2Dec 2, 2008
Circuit board design
INTEL CORP7 citations73
US10617000B2Apr 7, 2020
Printed circuit board (PCB) with three-dimensional interconnects to other printed circuit boards
INTEL CORP5 citations72
US7447929B2Nov 4, 2008
Countering power resonance
INTEL CORP8 citations72
US6717823B2Apr 6, 2004
Systems having modules with buffer chips
INTEL CORP7 citations72
US6674649B2Jan 6, 2004
Systems having modules sharing on module terminations
INTEL CORP7 citations72
US10839887B2Nov 17, 2020
Applying chip select for memory device identification and power management control
INTEL CORP3 citations71
US10541018B2Jan 21, 2020
DDR memory bus with a reduced data strobe signal preamble timespan
INTEL CORP2 citations70
US10963404B2Mar 30, 2021
High bandwidth DIMM
INTEL CORP0 citations63
US10033382B2Jul 24, 2018
Method and apparatus for dynamic memory termination
INTEL CORP1 citations63
US7010637B2Mar 7, 2006
Single-ended memory interface system
INTEL CORP6 citations63
US6918078B2Jul 12, 2005
Systems with modules sharing terminations
INTEL CORP4 citations63
US6631083B2Oct 7, 2003
Systems with modules and clocking therefore
INTEL CORP5 citations63
US6539449B1Mar 25, 2003
Capacitively loaded continuity module
INTEL CORP5 citations63
MCCALL JAMES A
3 patentsBAINS KULJIT S
1 patentTAHOE RES LTD
1 patentShowing the top 50 of 81 patents by PatentIndex Score.