Inventor
KINTER RYAN C
US29 patents
⚠️ This page may combine multiple inventors who share the name “KINTER RYAN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MIPS TECH INC
24 patentsUS6430655B1Aug 6, 2002
Scratchpad RAM memory accessible in parallel to a primary cache
MIPS TECH INC70 citations96
US7853777B2Dec 14, 2010
Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions
MIPS TECH INC43 citations92
US7752627B2Jul 6, 2010
Leaky-bucket thread scheduler in a multithreading microprocessor
MIPS TECH INC34 citations92
US7664936B2Feb 16, 2010
Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages
MIPS TECH INC26 citations92
US7660969B2Feb 9, 2010
Multithreading instruction scheduler employing thread group priorities
MIPS TECH INC17 citations92
US7657891B2Feb 2, 2010
Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
MIPS TECH INC18 citations92
US7558939B2Jul 7, 2009
Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
MIPS TECH INC21 citations92
US6836833B1Dec 28, 2004
Apparatus and method for discovering a scratch pad memory configuration
MIPS TECH INC43 citations91
US7681014B2Mar 16, 2010
Multithreading instruction scheduler employing thread group priorities
MIPS TECH INC11 citations84
US7627794B2Dec 1, 2009
Apparatus and method for discrete test access control of multiple cores
MIPS TECH INC14 citations84
US7613904B2Nov 3, 2009
Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler
MIPS TECH INC14 citations84
US7594089B2Sep 22, 2009
Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
MIPS TECH INC20 citations84
US7925859B2Apr 12, 2011
Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
MIPS TECH INC10 citations83
US7769958B2Aug 3, 2010
Avoiding livelock using intervention messages in multiple core processors
MIPS TECH INC8 citations83
US7707389B2Apr 27, 2010
Multi-ISA instruction fetch unit for a processor, and applications thereof
MIPS TECH INC12 citations83
US7657708B2Feb 2, 2010
Methods for reducing data cache access power in a processor using way selection bits
MIPS TECH INC11 citations83
US7315937B2Jan 1, 2008
Microprocessor instructions for efficient bit stream extractions
MIPS TECH INC17 citations81
US7650465B2Jan 19, 2010
Micro tag array having way selection bits for reducing data cache access power
MIPS TECH INC7 citations73
US7873810B2Jan 18, 2011
Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion
MIPS TECH INC3 citations58
US6961819B2Nov 1, 2005
Method and apparatus for redirection of operations between interfaces
MIPS TECH INC4 citations57
US7739455B2Jun 15, 2010
Avoiding livelock using a cache manager in multiple core processors
MIPS TECH INC0 citations52
US7711926B2May 4, 2010
Mapping system and method for instruction set processing
MIPS TECH INC0 citations52
US7509456B2Mar 24, 2009
Apparatus and method for discovering a scratch pad memory configuration
MIPS TECH INC0 citations48
US7634619B2Dec 15, 2009
Method and apparatus for redirection of operations between interfaces
MIPS TECH INC0 citations46