Inventor
NGUYEN TRUNG N
US85 patents
Patents
50 patentsUS10379943B2Aug 13, 2019
Management of foreground and background processes in a storage controller
IBM9 citations84
US9971508B2May 15, 2018
Invoking input/output (I/O) threads on processors to demote tracks from a cache
IBM5 citations84
US9753773B1Sep 5, 2017
Performance-based multi-mode task dispatching in a multi-processor core system for extreme temperature avoidance
IBM10 citations84
US9747139B1Aug 29, 2017
Performance-based multi-mode task dispatching in a multi-processor core system for high temperature avoidance
IBM14 citations84
US11321123B2May 3, 2022
Determining an optimum number of threads to make available per core in a multi-core processor complex to executive tasks
IBM5 citations73
US11157199B1Oct 26, 2021
Multi-mode address mapping management
IBM2 citations73
US11061818B1Jul 13, 2021
Recovering from write cache failures in servers
IBM2 citations73
US11003496B2May 11, 2021
Performance-based multi-mode task dispatching in a multi-processor core system for high temperature avoidance
IBM2 citations73
US10810304B2Oct 20, 2020
Injecting trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code
IBM3 citations73
US10528437B2Jan 7, 2020
Monitoring correctable errors on a bus interface to determine whether to redirect input/output request (I/O) traffic to another bus interface
IBM3 citations73
US10430264B2Oct 1, 2019
Monitoring correctable errors on a bus interface to determine whether to redirect input/output (I/O) traffic from a first processing unit to a second processing unit
IBM3 citations73
US10275280B2Apr 30, 2019
Reserving a core of a processor complex for a critical task
IBM6 citations73
US10169248B2Jan 1, 2019
Determining cores to assign to cache hostile tasks
IBM1 citations73
US10082958B2Sep 25, 2018
Invoking input/output (I/O) threads on processors to demote tracks from a cache
IBM3 citations73
US9971689B2May 15, 2018
Invoking input/output (I/O) threads and demote threads on processors to demote tracks from a cache
IBM2 citations73
US9952982B2Apr 24, 2018
Invoking demote threads on processors to demote tracks indicated in demote ready lists from a cache when a number of free cache segments in the cache is below a free cache segment threshold
IBM2 citations73
US9870275B2Jan 16, 2018
Processor thread management
IBM2 citations73
US9606835B1Mar 28, 2017
Determination of memory access patterns of tasks in a multi-core processor
IBM3 citations73
US11150944B2Oct 19, 2021
Balancing mechanisms in ordered lists of dispatch queues in a computational device
IBM6 citations72
US11029998B2Jun 8, 2021
Grouping of tasks for distribution among processing entities
IBM4 citations72
US10691502B2Jun 23, 2020
Task queuing and dispatching mechanisms in a computational device
IBM4 citations72
US10540170B2Jan 21, 2020
Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment
IBM1 citations72
US10528412B2Jan 7, 2020
Multiple path error data collection in a storage management system
IBM2 citations72
US10185593B2Jan 22, 2019
Balancing categorized task queues in a plurality of processing entities of a computational device
IBM3 citations72
US9852075B2Dec 26, 2017
Allocate a segment of a buffer to each of a plurality of threads to use for writing data
IBM2 citations72
US9842016B2Dec 12, 2017
Multiple path error data collection in a storage management system
IBM4 citations72
US9842010B1Dec 12, 2017
Adjustment of a sleep duration for a process based on an expected time for securing a spinlock
IBM4 citations72
US9571578B1Feb 14, 2017
Utilization based multi-buffer self-calibrated dynamic adjustment management
IBM6 citations72
US9483410B1Nov 1, 2016
Utilization based multi-buffer dynamic adjustment management
IBM3 citations72
US9442674B1Sep 13, 2016
Using a plurality of sub-buffers and a free segment list to allocate segments to a plurality of threads to use for writing data
IBM4 citations72
US10936369B2Mar 2, 2021
Maintenance of local and global lists of task control blocks in a processor-specific manner for allocation to tasks
IBM5 citations71
US10565020B2Feb 18, 2020
Adjustment of the number of central processing units to meet performance requirements of an I/O resource
IBM2 citations71
US11755735B2Sep 12, 2023
Speculatively executing conditional branches of code when detecting potentially malicious activity
IBM0 citations63
US11620219B2Apr 4, 2023
Storage drive dependent track removal in a cache for storage
IBM0 citations63
US11520631B2Dec 6, 2022
Determination of memory access patterns of tasks in a multi-core processor
IBM0 citations63
US11281502B2Mar 22, 2022
Dispatching tasks on processors based on memory access efficiency
IBM0 citations63
US11157355B2Oct 26, 2021
Management of foreground and background processes in a storage controller
IBM0 citations63
US11093399B2Aug 17, 2021
Selecting resources to make available in local queues for processors to use
IBM0 citations63
US11068418B2Jul 20, 2021
Determining memory access categories for tasks coded in a computer program
IBM0 citations63
US11061784B2Jul 13, 2021
Monitoring correctable errors on a bus interface to determine whether to redirect input/output request (I/O) traffic to another bus interface
IBM1 citations63
US11036635B2Jun 15, 2021
Selecting resources to make available in local queues for processors to use
IBM0 citations63
US11003777B2May 11, 2021
Determining a frequency at which to execute trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code
IBM1 citations63
US10956322B2Mar 23, 2021
Storage drive dependent track removal in a cache for storage
IBM0 citations63
US10949277B2Mar 16, 2021
Monitoring correctable errors on a bus interface to determine whether to redirect input/output (I/O) traffic from a first processing unit to a second processing unit
IBM1 citations63
US10223164B2Mar 5, 2019
Execution of critical tasks based on the number of available processing entities
IBM1 citations63
US10204060B2Feb 12, 2019
Determining memory access categories to use to assign tasks to processor cores to execute
IBM1 citations63
US11175948B2Nov 16, 2021
Grouping of tasks for distribution among processing entities
IBM0 citations62
US10996994B2May 4, 2021
Task queuing and dispatching mechanisms in a computational device
IBM0 citations62
US10956354B2Mar 23, 2021
Detecting a type of storage adapter connected and miscabling of a microbay housing the storage adapter
IBM0 citations62
US11354208B2Jun 7, 2022
Adjustment of safe data commit scan based on operational verification of non-volatile memory
IBM1 citations61
Showing the top 50 of 85 patents by PatentIndex Score.