Inventor

DEVTA-PRASANNA NARENDRA

IN6 patents

⚠️ This page may combine multiple inventors who share the name “DEVTA-PRASANNA NARENDRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI CORP

4 patents

US7461307B2Dec 2, 2008

System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop

LSI CORP12 citations81

US7293210B2Nov 6, 2007

System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flop

LSI CORP8 citations71

US7802159B1Sep 21, 2010

Enhanced logic built-in self-test module and method of online system testing employing the same

LSI CORP5 citations61

US7461315B2Dec 2, 2008

Method and system for improving quality of a circuit through non-functional test pattern identification

LSI CORP2 citations60

LSI LOGIC CORP

1 patent

US7555688B2Jun 30, 2009

Method for implementing test generation for systematic scan reconfiguration in an integrated circuit

LSI LOGIC CORP24 citations86

DEVTA-PRASANNA NARENDRA

1 patent

US8627160B2Jan 7, 2014

System and device for reducing instantaneous voltage droop during a scan shift operation

DEVTA-PRASANNA NARENDRA13 citations78