Inventor
LOGIOU MORGANE
FR3 patents
Patents
3 patentsUS12424995B2Sep 23, 2025
Method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge trapping layer
SOITEC SILICON ON INSULATOR0 citations55
US12445102B2Oct 14, 2025
Method for preparing a thin layer of ferroelectric material
SOITEC SILICON ON INSULATOR0 citations44
US11171256B2Nov 9, 2021
Process for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters
SOITEC SILICON ON INSULATOR0 citations40