Inventor
KELM JOHN H
US25 patents
⚠️ This page may combine multiple inventors who share the name “KELM JOHN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
APPLE INC
16 patentsUS10055369B1Aug 21, 2018
Systems and methods for coalescing interrupts
APPLE INC14 citations83
US11550745B1Jan 10, 2023
Remapping techniques for message signaled interrupts
APPLE INC4 citations74
US11720520B2Aug 8, 2023
Universal serial bus time synchronization
APPLE INC2 citations73
US10496572B1Dec 3, 2019
Intracluster and intercluster interprocessor interrupts including a retract interrupt that causes a previous interrupt to be canceled
APPLE INC3 citations72
US11594189B2Feb 28, 2023
Backlight reconstruction and compensation-based throttling
APPLE INC3 citations68
US11914521B1Feb 27, 2024
Cache quota control
APPLE INC3 citations66
US12332834B2Jun 17, 2025
Universal serial bus time synchronization
APPLE INC0 citations62
US11169585B2Nov 9, 2021
Dashboard with push model for receiving sensor data
APPLE INC0 citations62
US12321746B2Jun 3, 2025
DSB operation with excluded region
APPLE INC0 citations61
US11720360B2Aug 8, 2023
DSB operation with excluded region
APPLE INC0 citations61
US12360836B2Jul 15, 2025
Datalogging circuit triggered by a watchdog timer
APPLE INC0 citations59
US11853148B2Dec 26, 2023
Datalogging circuit triggered by a watchdog timer
APPLE INC0 citations59
US11842700B2Dec 12, 2023
Backlight reconstruction and compensation-based throttling
APPLE INC0 citations58
US11226752B2Jan 18, 2022
Filtering memory calibration
APPLE INC0 citations55
US12591294B1Mar 31, 2026
Performance states in integrated circuit
APPLE INC0 citations52
US11501820B2Nov 15, 2022
Selective reference voltage calibration in memory subsystem
APPLE INC0 citations51
INTEL CORP
5 patentsUS9612840B2Apr 4, 2017
Method and apparatus for implementing a dynamic out-of-order processor pipeline
INTEL CORP3 citations71
US10409763B2Sep 10, 2019
Apparatus and method for efficiently implementing a processor pipeline
INTEL CORP6 citations70
US9870209B2Jan 16, 2018
Instruction and logic for reducing data cache evictions in an out-of-order processor
INTEL CORP5 citations70
US9971599B2May 15, 2018
Instruction and logic for support of code modification
INTEL CORP2 citations68
US10338927B2Jul 2, 2019
Method and apparatus for implementing a dynamic out-of-order processor pipeline
INTEL CORP1 citations61