Inventor

KALTENBACH MARKUS

DE66 patents

⚠️ This page may combine multiple inventors who share the name “KALTENBACH MARKUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KALTENBACH MARKUS

IBM

Register files for storing data operated on by instructions of multiple widths

Register files for storing data operated on by instructions of multiple widths

Independent mapping of threads

Multi-engine address translation facility

Independent mapping of threads

Instructions to count contiguous register elements having a specific value in a selected location

Instructions to count contiguous register elements having a specific value in a selected location

Multi-engine address translation facility

Translating virtual memory addresses to physical addresses

Operating different processor cache levels

Instructions to count a number of contiguous register elements having specific values in a selected location

Instructions to count a number of contiguous register elements having specific values in a selected location

Operating different processor cache levels

Method and arrangement for saving cache power

Independent mapping of threads

Method and arrangement for saving cache power

Selective downstream cache processing for data access

Multi-engine address translation facility

Selective downstream cache processing for data access

Special tracking pool enhancement for core local cache address invalidates

Translation lookaside buffer purging with concurrent cache updates

Shadow pointer directory in an inclusive hierarchical cache

Method and system for changing a description for a state transition function of a state machine engine

Method and apparatus for an efficient TLB lookup

Multi-engine address translation facility

Multi-engine address translation facility

Independent mapping of threads

Fast normalization in a mixed precision floating-point unit

Fast normalization in a mixed precision floating-point unit

Method and arrangement for saving cache power

Filtering of redundantly scheduled write passes

Operating different processor cache levels

Method and arrangement for saving cache power

Selective downstream cache processing for data access

Selective downstream cache processing for data access

Integrated circuit chip and a method for testing the same

Operating different processor cache levels

Method and arrangement for saving cache power

Filtering of redundently scheduled write passes

Integrated circuit chip and a method for testing the same

Splitable and scalable normalizer for vector data

Integrated circuit chip and a method for testing the same

Splitable and scalable normalizer for vector data

BOERSMA MAARTEN J

Mechanism to speed-up multithreaded execution by register file write port reallocation

Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency

Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product

Apparatus and method for calculating an SHA-2 hash function in a general purpose processor

Splitable and scalable normalizer for vector data

KALTENBACH MARKUS

Code translation verification

LONOCLOUD INC

Systems, methods, and apparatus for improved application security