Inventor
GOVINDARAJU SRIDHAR
US18 patents
Patents
18 patentsUS10847423B2Nov 24, 2020
Techniques and configurations to reduce transistor gate short defects
INTEL CORP4 citations83
US9704798B2Jul 11, 2017
Using materials with different etch rates to fill trenches in semiconductor devices
INTEL CORP10 citations80
US7758238B2Jul 20, 2010
Temperature measurement with reduced extraneous infrared in a processing chamber
INTEL CORP8 citations80
US11217582B2Jan 4, 2022
Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
INTEL CORP2 citations72
US10468305B2Nov 5, 2019
Techniques and configurations to reduce transistor gate short defects
INTEL CORP2 citations72
US12094780B2Sep 17, 2024
Techniques and configurations to reduce transistor gate short defects
INTEL CORP0 citations62
US11756833B2Sep 12, 2023
Techniques and configurations to reduce transistor gate short defects
INTEL CORP0 citations62
US11688792B2Jun 27, 2023
Dual self-aligned gate endcap (SAGE) architectures
INTEL CORP0 citations62
US11605632B2Mar 14, 2023
Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
INTEL CORP0 citations62
US11380592B2Jul 5, 2022
Techniques and configurations to reduce transistor gate short defects
INTEL CORP0 citations62
US11205708B2Dec 21, 2021
Dual self-aligned gate endcap (SAGE) architectures
INTEL CORP0 citations62
US11705453B2Jul 18, 2023
Self-aligned gate endcap (SAGE) architecture having local interconnects
INTEL CORP0 citations60
US7892971B2Feb 22, 2011
Sub-second annealing processes for semiconductor devices
INTEL CORP5 citations59
US11329138B2May 10, 2022
Self-aligned gate endcap (SAGE) architecture having endcap plugs
INTEL CORP0 citations51
US9761497B2Sep 12, 2017
Techniques and configurations to reduce transistor gate short defects
INTEL CORP0 citations51
US9281401B2Mar 8, 2016
Techniques and configurations to reduce transistor gate short defects
INTEL CORP0 citations51
US7790587B2Sep 7, 2010
Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed thereby
INTEL CORP0 citations47
US11978776B2May 7, 2024
Non-planar semiconductor device having conforming ohmic contacts
INTEL CORP0 citations43