Inventor

PARTHASARATHY SIVAGNANAM

US233 patents

⚠️ This page may combine multiple inventors who share the name “PARTHASARATHY SIVAGNANAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARTHASARATHY SIVAGNANAM

MICRON TECHNOLOGY INC

Self adapting iterative read calibration to retrieve data from memory cells

Intelligent proactive responses to operations to read data from memory cells

Detection of an incorrectly located read voltage

Compound feature generation in classification of error rate of data retrieved from memory cells

Error correction with syndrome computation in a memory device

Read soft bits through boosted modulation following reading hard bits

Compound feature generation in classification of error rate of data retrieved from memory cells

Voltage bin selection for blocks of a memory device after power up of the memory device

Self adapting iterative read calibration to retrieve data from memory cells

Determine optimized read voltage via identification of distribution shape of signal and noise characteristics

Bit flipping low-density parity-check decoders with low error floor

Reading of soft bits and hard bits from memory cells

Memory system performance enhancements using measured signal and noise characteristics of memory cells

Determine bit error count based on signal and noise characteristics centered at an optimized read voltage

Adaptive and/or iterative operations in executing a read command to retrieve data from memory cells

Operating temperature management of a memory sub-system

Compute an optimized read voltage

Error correction based on rate adaptive low density parity check (LDPC) codes with flexible column weights in the parity check matrices

Optimization of soft bit windows based on signal and noise characteristics of memory cells

Tiered error correction code (ECC) operations in memory

Redundant array of independent NAND for a three-dimensional memory array

Error correction code (ECC) operations in memory for providing redundant error correction

Estimating an error rate associated with memory

Determining soft data from a hard read

Configuring iterative error correction parameters using criteria from previous iterations

Error correction methods and apparatuses using first and second decoders

Performing a test of memory components with fault tolerance

Iterative decoder with a dynamic maximum stop condition

Voltage bin selection for blocks of a memory device after power up of the memory device

Intelligent proactive responses to operations to read data from memory cells

Managing voltage bin selection for blocks of a memory device

Managing compensation for charge coupling and lateral migration in memory devices

Detection of an incorrectly located read voltage

Classification of error rate of data retrieved from memory cells

Adjustment of code rate as function of memory endurance state metric

Methods for performing processing-in-memory operations, and related memory devices and systems

Multi-layer code rate architecture for copyback between partitions with different code rates

Spatiotemporal fused-multiply-add, and related systems, methods and devices

Adaptive and/or iterative operations in executing a read command to retrieve data from memory cells

Self adapting iterative read calibration to retrieve data from memory cells

Dynamic adjustment of data integrity operations of a memory system based on error rate classification

Compound feature generation in classification of error rate of data retrieved from memory cells

ST MICROELECTRONICS INC

System and method for managing vertical dependencies in a digital signal processor

System and method for dynamically sizing hardware loops and executing nested loops in a digital signal processor

Apparatus and method for implementing a ROM patch using a lockable cache

Coprocessor extension architecture built using a novel split-instruction transaction model

IBM

Power management initialization for a computer operable under a plurality of operating systems

EDGESTREAM INC

Re-assembly of streaming files from separate connections

PARTHASARATHY SIVAGNANAM

Determining whether a memory cell state is in a valley between adjacent data states

ST MICROELECTRONICS SA

Executing cache instructions in an increased latency mode