Inventor

KHAYAT PATRICK R

US77 patents

⚠️ This page may combine multiple inventors who share the name “KHAYAT PATRICK R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHAYAT PATRICK R

MICRON TECHNOLOGY INC

Error correction with syndrome computation in a memory device

Providing data of a memory system based on an adjustable error rate

Tiered error correction code (ECC) operations in memory

Error correction code (ECC) operations in memory for providing redundant error correction

Estimating an error rate associated with memory

Determining soft data from a hard read

Adjusting a parameter for a programming operation based on the temperature of a memory system

Managing compensation for charge coupling and lateral migration in memory devices

Tiered error correction code (ECC) operations in memory

Memory cell state in a valley between adjacent data states

Estimating an error rate associated with memory

Apparatuses and methods for generating probabilistic information with current integration sensing

Determining whether a memory cell state is in a valley between adjacent data states

Area efficient implementation of a product code error correcting code decoder

Managing compensation for charge coupling and lateral migration in memory devices

Temperature-compensated time estimate for a block to reach a uniform charge loss state

Measurement of representative charge loss in a block to determine charge loss state

Managing program verify voltage offsets for charge coupling and lateral migration compensation in memory devices

Error correction with syndrome computation in a memory device

Temperature-compensated time estimate for a block to reach a uniform charge loss state

Measurement of representative charge loss in a block to determine charge loss state

Providing data of a memory system based on an adjustable error rate

Error correction code (ECC) operations in memory for providing redundant error correction

Tiered error correction code (ECC) operations in memory

Stopping criteria for layered iterative error correction

Estimating an error rate associated with memory

Providing data of a memory system based on an adjustable error rate

Determining soft data for fractional digit memory cells

Stopping criteria for layered iterative error correction

Error correction code (ECC) operations in memory for providing redundant error correction

Apparatuses and methods for generating probabilistic information with current integration sensing

Determining soft data from a hard read

Determining soft data for fractional digit memory cells

Stopping criteria for layered iterative error correction

Dual mapping between program states and data patterns

Memory device producing metadata characterizing applied read voltage level with respect to voltage distributions

Adaptive integrity scan rates in a memory sub-system based on block health metrics

Validating read level voltage in memory devices

Using duplicate data for improving error correction capability

Two-sided page scans with calibration feedback

Using duplicate data for improving error correction capability

Memory cell state in a valley between adjacent data states

High throughput bit correction of data inside a word buffer for a product code decoder

Accessing data using error correction operation(s) to reduce latency at a memory sub-system

Accessing data using error correction operation(s) to reduce latency at a memory sub-system

Adjusting a parameter for a programming operation based on the temperature of a memory system

Error-handling with multiple levels of decoders

KAYNAK MUSTAFA N

Rendering data write errors detectable

Detecting data-write errors

PARTHASARATHY SIVAGNANAM

Determining whether a memory cell state is in a valley between adjacent data states