Inventor

KAYNAK MUSTAFA N

US152 patents

⚠️ This page may combine multiple inventors who share the name “KAYNAK MUSTAFA N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAYNAK MUSTAFA N

MICRON TECHNOLOGY INC

Bin placement according to program-erase cycles

Error correction with syndrome computation in a memory device

Voltage bin selection for blocks of a memory device after power up of the memory device

Managing bin placement for block families of a memory device based on trigger metric values

Bit flipping low-density parity-check decoders with low error floor

Block family combination and voltage bin selection

Error correction based on rate adaptive low density parity check (LDPC) codes with flexible column weights in the parity check matrices

Voltage offset bin selection by die group for memory devices

Performing threshold voltage offset bin selection by package for memory devices

Providing data of a memory system based on an adjustable error rate

Tiered error correction code (ECC) operations in memory

Error correction code (ECC) operations in memory for providing redundant error correction

Estimating an error rate associated with memory

Determining soft data from a hard read

Adjusting a parameter for a programming operation based on the temperature of a memory system

Iterative decoder with a dynamic maximum stop condition

Block family-based error avoidance for memory devices

Voltage bin selection for blocks of a memory device after power up of the memory device

Managing voltage bin selection for blocks of a memory device

Managing compensation for charge coupling and lateral migration in memory devices

Adjustment of code rate as function of memory endurance state metric

Multi-layer code rate architecture for copyback between partitions with different code rates

Multi-tier threshold voltage offset bin calibration

Managing error-handling flows in memory devices

Methods and systems of stall mitigation in iterative decoders

Managing workload of programming sets of pages to memory device

Voltage calibration scans to reduce memory device overhead

Multi-tier threshold voltage offset bin calibration

Error avoidance based on voltage distribution parameters of block families

Voltage bin calibration based on a temporary voltage shift offset

Managing defective bitline locations in a bit flipping decoder

Selective partitioning of sets of pages programmed to memory device

Descrambling of scrambled linear codewords using non-linear scramblers

Block family-based error avoidance for memory devices

Extended cross-temperature handling in a memory sub-system

Tiered error correction code (ECC) operations in memory

Memory cell state in a valley between adjacent data states

Estimating an error rate associated with memory

Apparatuses and methods for generating probabilistic information with current integration sensing

Determining whether a memory cell state is in a valley between adjacent data states

Memory compaction management in memory devices

Early stopping of bit-flip low density parity check decoding based on syndrome weight

Managing compensation for charge coupling and lateral migration in memory devices

Dynamic adjustment of offset voltages for reading memory cells in a memory device

Detecting a stall condition in bit flipping decoding using syndrome weight slope

Adjustment of code rate as function of memory endurance state metric

Block family-based error avoidance for memory devices

KAYNAK MUSTAFA N

Rendering data write errors detectable

Detecting data-write errors

PARTHASARATHY SIVAGNANAM

Determining whether a memory cell state is in a valley between adjacent data states