Inventor

SUBRAMONEY SREENIVAS

IN80 patents

⚠️ This page may combine multiple inventors who share the name “SUBRAMONEY SREENIVAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUBRAMONEY SREENIVAS

INTEL CORP

Method and system performing concurrently mark-sweep garbage collection invoking garbage collection thread to track and mark live objects in heap block using bit vector

Method for using non-temporal streaming to improve garbage collection algorithm

Method for using cache prefetch feature to improve garbage collection algorithm

High end imaging radar

Dynamic performance monitoring-based approach to memory management

Application programming interface for fine grained low latency decompression within processor core

Cryptographic computing engine for memory load and store units of a microarchitecture pipeline

Technology for dynamically tuning processor features

Memory-efficient last level cache architecture

Memory-efficient last level cache architecture

Data relocation for inline metadata

Apparatuses, methods, and systems for dual spatial pattern prefetcher

Supporting timely and context triggered prefetching in microprocessors

Automatic predication of hard-to-predict convergent branches

Misprediction-triggered local history-based branch prediction

Efficient hardware-based extraction of program instructions for critical paths

Dynamic detection and prediction for store-dependent branches

Branch predictor with empirical branch bias override

Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time

Partner-aware virtual microsectoring for sectored cache architectures

System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processor

Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects

Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis

Maintaining contiguity of virtual to physical address mappings to exploit contiguity-aware translation look-aside buffer hardware

Instruction and micro-architecture support for decompression on core

Restoring persistent application data from non-volatile memory after a system crash or system reboot

Technology for dynamically tuning processor features

Detecting a dynamic control flow re-convergence point for conditional branches in hardware

Technology for dynamically tuning processor features

Criticality based port scheduling

System, apparatus and method for context-based override of history-based branch predictions

Methods and apparatus to profile page tables for memory management

Apparatuses, methods, and systems for a duplication resistant on-die irregular data prefetcher

Spatially sparse neural network accelerator for multi-dimension visual analytics

Spatially sparse neural network accelerator for multi-dimension visual analytics

High bandwidth destructive read embedded memory

Memory aware reordered source

Adaptive spatial access prefetcher apparatus and method

De-prioritizing speculative code lines in on-chip caches

System, method, and apparatus for enhanced pointer identification and prefetching

Loop support extensions

System, method, and apparatus for enhanced pointer identification and prefetching

System, method, and apparatus for enhanced pointer identification and prefetching

Point cloud adjacency-map and hash-map accelerator

Method and apparatus for leveraging simultaneous multithreading for bulk compute operations

Throttling code fetch for speculative code paths

Selecting keypoints in images using descriptor scores

Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP)

SUBRAMANIAN LAVANYA

Coordinated thread criticality-aware memory scheduling

KUMAR AMIT

Identifying and prioritizing critical instructions within processor circuitry