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Inventor

BURGESS BRADLEY GENE

US11 patents
⚠️ This page may combine multiple inventors who share the name “BURGESS BRADLEY GENE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIFIVE INC

7 patents
US12530197B2Jan 20, 2026

Vector instruction processing after primary decode

SIFIVE INC0 citations61
US12524352B2Jan 13, 2026

Cache replacement policy state structure with extra states for prefetch and non-temporal loads

SIFIVE INC0 citations59
US12493465B2Dec 9, 2025

Vector load store operations in a vector pipeline using a single operation in a load store unit

SIFIVE INC0 citations59
US12293192B2May 6, 2025

Bundling and dynamic allocation of register blocks for vector instructions

SIFIVE INC0 citations59
US12204458B1Jan 21, 2025

Translation lookaside buffer probing prevention

SIFIVE INC0 citations59
US12554504B2Feb 17, 2026

Dependency tracking and chaining for vector instructions

SIFIVE INC0 citations50
US12373210B2Jul 29, 2025

Transfer buffer between a scalar pipeline and vector pipeline

SIFIVE INC0 citations44

SAMSUNG ELECTRONICS CO LTD

2 patents
US9395988B2Jul 19, 2016

Micro-ops including packed source and destination fields

SAMSUNG ELECTRONICS CO LTD2 citations60
US9424041B2Aug 23, 2016

Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions

SAMSUNG ELECTRONICS CO LTD2 citations58

BURGESS BRADLEY GENE

1 patent
US9588770B2Mar 7, 2017

Dynamic rename based register reconfiguration of a vector register file

BURGESS BRADLEY GENE2 citations65

DENMAN MARVIN

1 patent
US9836304B2Dec 5, 2017

Cumulative confidence fetch throttling

DENMAN MARVIN5 citations63