Inventor

HOROWITZ MARK

US76 patents

⚠️ This page may combine multiple inventors who share the name “HOROWITZ MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOROWITZ MARK

RAMBUS INC

Memory module including an integrated circuit device

Integrated circuit device having double data rate capability

Memory device having a programmable register

Memory device having a programmable register

Memory device which samples data after an amount of time transpires

Synchronous memory device having automatic precharge

System having double data transfer rate and intergrated circuit therefor

Memory device having write latency

Method of operating a memory device having write latency

Method and apparatus for controlling a synchronous memory device

Memory system including a plurality of memory devices and a transceiver device

Method of operating a memory device having a variable data input length

Method of operating a synchronous memory device

Synchronous memory device having a delay time register and method of operating same

Method of operating a memory having a variable data output length and a programmable register

Dual clocked synchronous memory device having a delay time register and method of operating same

Method of operating a synchronous memory device having a variable data output length

Synchronous memory device utilizing two external clocks

Synchronous memory device having an internal register

Synchronous memory device having a programmable register and method of controlling same

Memory module having memory devices containing internal device ID registers and method of initializing same

Integrated circuit I/O using a high performance bus interface

Integrated circuit I/O using a high performance bus interface

Memory device with a phase locked loop circuitry

Integrated circuit I/O using a high performance bus interface

Memory circuitry having bus interface for receiving information in packets and access time registers

Integrated circuit I/O using a high performance bus interface

Integrated circuit I/O using a high performance bus interface

Integrated circuit I/O using high performance bus interface

Apparatus for synchronously generating clock signals in a data processing system

Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals

Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals

Method and apparatus for calibrating a multi-level current mode driver

Memory device having a variable data output length and a programmable register

Synchronous memory device

Integrated circuit I/O using a high performance bus interface

Synchronous memory device having automatic precharge

Method of operating a memory device having a variable data input length

Memory device having a plurality of programmable internal registers and a delay time register

Method of operation of a memory controller

Method of operating a memory device having a variable data output length and an identification register

System having a synchronous memory device

Integrated circuit having memory which synchronously samples information with respect to external clock signals

Integrated circuit I/O using a high performance bus interface

Method for accessing and transmitting data to/from a memory in packets

Integrated circuit I/O using a high performance bus interface

Integrated circuit device which outputs data after a latency period transpires

Memory device having a variable data output length

Synchronous memory device utilizing request protocol and method of operation of same

UNIV LELAND STANFORD JUNIOR

Apparatus and method for capturing a scene using staggered triggering of dense camera arrays