Inventor
POGGE H BERNHARD
US37 patents
Patents
37 patentsUS7354798B2Apr 8, 2008
Three-dimensional device fabrication method
IBM285 citations99
US6599778B2Jul 29, 2003
Chip and wafer integration process using vertical connections
IBM495 citations99
US6355501B1Mar 12, 2002
Three-dimensional chip stacking assembly
IBM802 citations99
US6864165B1Mar 8, 2005
Method of fabricating integrated electronic chip with an interconnect device
IBM83 citations98
US6110806AAug 29, 2000
Process for precision alignment of chips for mounting on a substrate
IBM124 citations98
US6856025B2Feb 15, 2005
Chip and wafer integration process using vertical connections
IBM35 citations96
US6835589B2Dec 28, 2004
Three-dimensional integrated CMOS-MEMS device and process for making the same
IBM48 citations96
US6444560B1Sep 3, 2002
Process for making fine pitch connections between devices and structure made by the process
IBM65 citations96
US6429045B1Aug 6, 2002
Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage
IBM74 citations96
US6087199AJul 11, 2000
Method for fabricating a very dense chip package
IBM58 citations96
US5814885ASep 29, 1998
Very dense integrated circuit package
IBM64 citations96
US6066513AMay 23, 2000
Process for precise multichip integration and product thereof
IBM98 citations95
US5899703AMay 4, 1999
Method for chip testing
IBM51 citations95
US7564118B2Jul 21, 2009
Chip and wafer integration process using vertical connections
IBM23 citations93
US7388277B2Jun 17, 2008
Chip and wafer integration process using vertical connections
IBM20 citations93
US7344959B1Mar 18, 2008
Metal filled through via structure for providing vertical wafer-to-wafer interconnection
IBM39 citations93
US7071031B2Jul 4, 2006
Three-dimensional integrated CMOS-MEMS device and process for making the same
IBM42 citations93
US7049697B2May 23, 2006
Process for making fine pitch connections between devices and structure made by the process
IBM22 citations93
US6737297B2May 18, 2004
Process for making fine pitch connections between devices and structure made by the process
IBM32 citations93
US6640021B2Oct 28, 2003
Fabrication of a hybrid integrated circuit device including an optoelectronic chip
IBM47 citations93
US6460265B2Oct 8, 2002
Double-sided wafer exposure method and device
IBM27 citations93
US6333553B1Dec 25, 2001
Wafer thickness compensation for interchip planarity
IBM16 citations93
US5998868ADec 7, 1999
Very dense chip package
IBM45 citations93
US5681775AOct 28, 1997
Soi fabrication process
IBM36 citations93
US5866443AFeb 2, 1999
Very dense integrated circuit package and method for forming the same
IBM26 citations91
US5770884AJun 23, 1998
Very dense integrated circuit package
IBM33 citations91
US5081439AJan 14, 1992
Thin film resistor and method for producing same
IBM33 citations91
US6025638AFeb 15, 2000
Structure for precision multichip assembly
IBM35 citations89
US4137103AJan 30, 1979
Silicon integrated circuit region containing implanted arsenic and germanium
IBM32 citations89
US4111719ASep 5, 1978
Minimization of misfit dislocations in silicon by double implantation of arsenic and germanium
IBM32 citations89
US7821120B2Oct 26, 2010
Metal filled through via structure for providing vertical wafer-to-wafer interconnection
IBM11 citations84
US7049695B1May 23, 2006
Method and device for heat dissipation in semiconductor modules
IBM13 citations84
US6548325B2Apr 15, 2003
Wafer thickness compensation for interchip planarity
IBM6 citations74
US6730529B1May 4, 2004
Method for chip testing
IBM8 citations73
US3961353AJun 1, 1976
High power semiconductor device
IBM11 citations70
US4006045AFeb 1, 1977
Method for producing high power semiconductor device using anodic treatment and enhanced diffusion
IBM6 citations59
US8367543B2Feb 5, 2013
Structure and method to improve current-carrying capabilities of C4 joints
IBM0 citations37