Inventor

EBRAHIM ZAHIR

US27 patents

⚠️ This page may combine multiple inventors who share the name “EBRAHIM ZAHIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EBRAHIM ZAHIR

SUN MICROSYSTEMS INC

System for context-dependent name resolution

Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU)

Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system

System and method for preserving message order while employing both programmed I/O and DMA operations

Power sequence controller with wakeup logic for enabling a wakeup interrupt handler procedure

Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system

Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system

Apparatus and method for fast filtering read and write barrier operations in garbage collection system

Method and apparatus for reducing power consumption in a computer network without sacrificing performance

Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system

Packet switched cache coherent multiprocessor system

System and method for swapping blocks of tagged stack entries between a tagged stack cache and an untagged main memory storage

Garbage collection system and method for locating root set pointers in method activation records

Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system

System for multisized bus coupling in a packet-switched computer system

Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system

Method and apparatus for interrupt communication in a packet-switched computer system

Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor

System for multisized bus coupling in a packet-switched computer system

Method and apparatus for flow control in packet-switched computer system

System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO

Pipelined distributed bus arbitration system

Cache coherent computer system that minimizes invalidation and copyback operations

Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system

Pipelined distributed bus arbitration system

System level mechanism for invalidating data stored in the external cache of a processor in a computer system

SUN MIROSYSTEMS INC

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