Inventor

NISHTALA SATYANARAYANA

US37 patents

⚠️ This page may combine multiple inventors who share the name “NISHTALA SATYANARAYANA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NISHTALA SATYANARAYANA

SUN MICROSYSTEMS INC

Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system

Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system

Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system

Method and apparatus for reducing power consumption in a computer network without sacrificing performance

Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system

Packet switched cache coherent multiprocessor system

Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system

System for multisized bus coupling in a packet-switched computer system

Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system

Method and apparatus for interrupt communication in a packet-switched computer system

Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor

Stacking heatpipe for three dimensional electronic packaging

Computer system cooling configuration

System for dynamic ordering support in a ringlet serial interconnect

System for multisized bus coupling in a packet-switched computer system

System for dynamic ordering support in a ringlet serial interconnect

Method and apparatus for flow control in packet-switched computer system

Pipelined distributed bus arbitration system

Cache coherent computer system that minimizes invalidation and copyback operations

Source synchronization data transfers without resynchronization penalty

Composite DMA disk controller for efficient hardware-assisted data transfer operations

Method and system for data movement in data storage systems employing parcel-based data mapping

Apparatus and method for error detection on source-synchronous buses

Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system

Pipelined distributed bus arbitration system

Computer system with a shared address bus and pipelined write operations

System level mechanism for invalidating data stored in the external cache of a processor in a computer system

Method and apparatus for defining signal timing for an integrated circuit device

CISCO TECH INC

Input-output module, processing platform and method for extending a memory interface for input-output operations

Serial attached storage drive virtualization

System and methods for memory expansion

MAZZOLA MARIO

System and methods for memory expansion

System and methods for memory expansion

System and methods for memory expansion

NISHTALA SATYANARAYANA

Input-output module for operation in memory module socket and method for extending a memory interface for input-output operations

Method and apparatus for providing power to a server platforms by using a capacitor to provide power during a second power supply transitioning on

Server power manager and method for dynamically managing server power consumption