Inventor
NORMOYLE KEVIN
US27 patents
⚠️ This page may combine multiple inventors who share the name “NORMOYLE KEVIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SUN MICROSYSTEMS INC
14 patentsUS5905998AMay 18, 1999
Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system
SUN MICROSYSTEMS INC176 citations99
US5655100AAug 5, 1997
Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system
SUN MICROSYSTEMS INC288 citations99
US5644753AJul 1, 1997
Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
SUN MICROSYSTEMS INC164 citations99
US5684977ANov 4, 1997
Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
SUN MICROSYSTEMS INC104 citations98
US5634068AMay 27, 1997
Packet switched cache coherent multiprocessor system
SUN MICROSYSTEMS INC147 citations98
US5657472AAug 12, 1997
Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor
SUN MICROSYSTEMS INC95 citations96
US6535966B1Mar 18, 2003
System and method for using a page tracking buffer to reduce main memory latency in a computer system
SUN MICROSYSTEMS INC25 citations92
US5893153AApr 6, 1999
Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control
SUN MICROSYSTEMS INC67 citations91
US5706463AJan 6, 1998
Cache coherent computer system that minimizes invalidation and copyback operations
SUN MICROSYSTEMS INC51 citations91
US5761708AJun 2, 1998
Apparatus and method to speculatively initiate primary memory accesses
SUN MICROSYSTEMS INC42 citations89
US6446168B1Sep 3, 2002
Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity
SUN MICROSYSTEMS INC18 citations83
US5894587AApr 13, 1999
Multiple bus bridge system for maintaining a complete order by delaying servicing interrupts while posting write requests
SUN MICROSYSTEMS INC11 citations69
US5737755AApr 7, 1998
System level mechanism for invalidating data stored in the external cache of a processor in a computer system
SUN MICROSYSTEMS INC1 citations51
US7143304B2Nov 28, 2006
Method and apparatus for enhancing the speed of a synchronous bus
SUN MICROSYSTEMS INC0 citations50
ADVANCED MICRO DEVICES INC
6 patentsUS9448930B2Sep 20, 2016
Memory heaps in a memory model for a unified computing system
ADVANCED MICRO DEVICES INC5 citations84
US9116809B2Aug 25, 2015
Memory heaps in a memory model for a unified computing system
ADVANCED MICRO DEVICES INC3 citations74
US11741019B2Aug 29, 2023
Memory pools in a memory model for a unified computing system
ADVANCED MICRO DEVICES INC1 citations73
US11119944B2Sep 14, 2021
Memory pools in a memory model for a unified computing system
ADVANCED MICRO DEVICES INC1 citations73
US9965392B2May 8, 2018
Managing coherent memory between an accelerated processing device and a central processing unit
ADVANCED MICRO DEVICES INC2 citations73
US10324860B2Jun 18, 2019
Memory heaps in a memory model for a unified computing system
ADVANCED MICRO DEVICES INC0 citations52
ASARO ANTHONY
4 patentsUS9430391B2Aug 30, 2016
Managing coherent memory between an accelerated processing device and a central processing unit
ASARO ANTHONY1 citations50
US9009419B2Apr 14, 2015
Shared memory space in a unified memory model
ASARO ANTHONY0 citations50
US8984511B2Mar 17, 2015
Visibility ordering in a memory model for a unified computing system
ASARO ANTHONY0 citations50
US8935475B2Jan 13, 2015
Cache management for memory operations
ASARO ANTHONY1 citations50