Inventor
PALANCA SALVADOR
US30 patents
⚠️ This page may combine multiple inventors who share the name “PALANCA SALVADOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
25 patentsUS6842180B1Jan 11, 2005
Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor
INTEL CORP92 citations97
US6216215B1Apr 10, 2001
Method and apparatus for senior loads
INTEL CORP95 citations97
US6202129B1Mar 13, 2001
Shared cache structure for temporal and non-temporal information using indicative bits
INTEL CORP94 citations97
US6651151B2Nov 18, 2003
MFENCE and LFENCE micro-architectural implementation method and system
INTEL CORP42 citations96
US6546462B1Apr 8, 2003
CLFLUSH micro-architectural implementation method and system
INTEL CORP54 citations96
US6223258B1Apr 24, 2001
Method and apparatus for implementing non-temporal loads
INTEL CORP77 citations96
US6122715ASep 19, 2000
Method and system for optimizing write combining performance in a shared buffer structure
INTEL CORP84 citations96
US6073210AJun 6, 2000
Synchronization of weakly ordered write combining operations using a fencing mechanism
INTEL CORP76 citations96
US6801208B2Oct 5, 2004
System and method for cache sharing
INTEL CORP108 citations95
US6643745B1Nov 4, 2003
Method and apparatus for prefetching data into cache
INTEL CORP93 citations95
US6772291B2Aug 3, 2004
Method and apparatus for cache replacement for a multiple variable-way associative cache
INTEL CORP16 citations93
US6678810B1Jan 13, 2004
MFENCE and LFENCE micro-architectural implementation method and system
INTEL CORP15 citations93
US6665775B1Dec 16, 2003
Cache dynamically configured for simultaneous accesses by multiple computing engines
INTEL CORP37 citations93
US6845432B2Jan 18, 2005
Low power cache architecture
INTEL CORP44 citations92
US6735712B1May 11, 2004
Dynamically configurable clocking scheme for demand based resource sharing with multiple clock crossing domains
INTEL CORP20 citations92
US6584547B2Jun 24, 2003
Shared cache structure for temporal and non-temporal instructions
INTEL CORP26 citations92
US6526499B2Feb 25, 2003
Method and apparatus for load buffers
INTEL CORP17 citations92
US6205520B1Mar 20, 2001
Method and apparatus for implementing non-temporal stores
INTEL CORP38 citations92
US6173393B1Jan 9, 2001
System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data
INTEL CORP133 citations92
US6438658B1Aug 20, 2002
Fast invalidation scheme for caches
INTEL CORP32 citations91
US7136984B2Nov 14, 2006
Low power cache architecture
INTEL CORP23 citations89
US6434673B1Aug 13, 2002
Optimized configurable scheme for demand based resource sharing of request queues in a cache controller
INTEL CORP14 citations84
US9342310B2May 17, 2016
MFENCE and LFENCE micro-architectural implementation method and system
INTEL CORP5 citations80
US6782455B2Aug 24, 2004
Optimized configurable scheme for demand based resource sharing of request queues in a cache controller
INTEL CORP6 citations73
US6889291B1May 3, 2005
Method and apparatus for cache replacement for a multiple variable-way associative cache
INTEL CORP3 citations63
PALANCA SALVADOR
5 patentsUS9612835B2Apr 4, 2017
MFENCE and LFENCE micro-architectural implementation method and system
PALANCA SALVADOR3 citations84
US9383998B2Jul 5, 2016
MFENCE and LFENCE micro-architectural implementation method and system
PALANCA SALVADOR3 citations84
US8959314B2Feb 17, 2015
MFENCE and LFENCE micro-architectural implementation method and system
PALANCA SALVADOR6 citations83
US9098268B2Aug 4, 2015
MFENCE and LFENCE micro-architectural implementation method and system
PALANCA SALVADOR3 citations73
US8171261B2May 1, 2012
Method and system for accessing memory in parallel computing using load fencing instructions
PALANCA SALVADOR4 citations73