Inventor
PENTKOVSKI VLADIMIR
US33 patents
⚠️ This page may combine multiple inventors who share the name “PENTKOVSKI VLADIMIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
32 patentsUS6377970B1Apr 23, 2002
Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry
INTEL CORP173 citations99
US5995122ANov 30, 1999
Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format
INTEL CORP112 citations98
US6292815B1Sep 18, 2001
Data conversion between floating point packed format and integer scalar format
INTEL CORP98 citations97
US6202129B1Mar 13, 2001
Shared cache structure for temporal and non-temporal information using indicative bits
INTEL CORP94 citations97
US6502115B2Dec 31, 2002
Conversion between packed floating point data and packed 32-bit integer data in different architectural registers
INTEL CORP50 citations96
US6266769B1Jul 24, 2001
Conversion between packed floating point data and packed 32-bit integer data in different architectural registers
INTEL CORP49 citations96
US6263426B1Jul 17, 2001
Conversion from packed floating point data to packed 8-bit integer data in different architectural registers
INTEL CORP55 citations96
US6247116B1Jun 12, 2001
Conversion from packed floating point data to packed 16-bit integer data in different architectural registers
INTEL CORP69 citations96
US6243803B1Jun 5, 2001
Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry
INTEL CORP66 citations96
US6223258B1Apr 24, 2001
Method and apparatus for implementing non-temporal loads
INTEL CORP77 citations96
US6192467B1Feb 20, 2001
Executing partial-width packed data instructions
INTEL CORP82 citations96
US6122715ASep 19, 2000
Method and system for optimizing write combining performance in a shared buffer structure
INTEL CORP84 citations96
US6073210AJun 6, 2000
Synchronization of weakly ordered write combining operations using a fencing mechanism
INTEL CORP76 citations96
US6801208B2Oct 5, 2004
System and method for cache sharing
INTEL CORP108 citations95
US6643745B1Nov 4, 2003
Method and apparatus for prefetching data into cache
INTEL CORP93 citations95
US6122725ASep 19, 2000
Executing partial-width packed data instructions
INTEL CORP65 citations95
US6976131B2Dec 13, 2005
Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
INTEL CORP54 citations93
US6085312AJul 4, 2000
Method and apparatus for handling imprecise exceptions
INTEL CORP50 citations93
US7516307B2Apr 7, 2009
Processor for computing a packed sum of absolute differences and packed multiply-add
INTEL CORP18 citations92
US6978357B1Dec 20, 2005
Method and apparatus for performing cache segment flush and cache segment invalidation operations
INTEL CORP32 citations92
US6584547B2Jun 24, 2003
Shared cache structure for temporal and non-temporal instructions
INTEL CORP26 citations92
US6480868B2Nov 12, 2002
Conversion from packed floating point data to packed 8-bit integer data in different architectural registers
INTEL CORP37 citations92
US6356270B2Mar 12, 2002
Efficient utilization of write-combining buffers
INTEL CORP40 citations92
US6205520B1Mar 20, 2001
Method and apparatus for implementing non-temporal stores
INTEL CORP38 citations92
US7216138B2May 8, 2007
Method and apparatus for floating point operations and format conversion operations
INTEL CORP40 citations91
US6970994B2Nov 29, 2005
Executing partial-width packed data instructions
INTEL CORP12 citations84
US7467286B2Dec 16, 2008
Executing partial-width packed data instructions
INTEL CORP8 citations74
US6275904B1Aug 14, 2001
Cache pollution avoidance instructions
INTEL CORP14 citations74
US6223276B1Apr 24, 2001
Pipelined processing of short data streams using data prefetching
INTEL CORP13 citations73
US6748512B2Jun 8, 2004
Method and apparatus for mapping address space of integrated programmable devices within host system memory
INTEL CORP10 citations72
US6369813B2Apr 9, 2002
Processing polygon meshes using mesh pool window
INTEL CORP13 citations72
US9632790B2Apr 25, 2017
Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order
INTEL CORP2 citations64