Inventor

MAIYURAN SUBRAMANIAM

US240 patents

⚠️ This page may combine multiple inventors who share the name “MAIYURAN SUBRAMANIAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAIYURAN SUBRAMANIAM

INTEL CORP

Memory access latency hiding with hint buffer

Systems and methods for improving cache efficiency and utilization

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Sparse optimizations for a matrix accelerator architecture

Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor

Method and apparatus for senior loads

MFENCE and LFENCE micro-architectural implementation method and system

CLFLUSH micro-architectural implementation method and system

Method and system for optimizing write combining performance in a shared buffer structure

Synchronization of weakly ordered write combining operations using a fencing mechanism

System and method for cache sharing

Method and apparatus for prefetching data into cache

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Graphics processor sub-domain voltage regulation

Method and apparatus for a stew-based loop predictor

Method and apparatus for cache replacement for a multiple variable-way associative cache

MFENCE and LFENCE micro-architectural implementation method and system

Cache dynamically configured for simultaneous accesses by multiple computing engines

Charge sharing and charge recycling for an on-chip bus

Dynamically configurable clocking scheme for demand based resource sharing with multiple clock crossing domains

Method and apparatus for load buffers

Efficient utilization of write-combining buffers

Method and apparatus for implementing non-temporal stores

Software scoreboard information and synchronization

Fast invalidation scheme for caches

Method and apparatus for the implementation of full-scene anti-aliasing supersampling

Graphics processor data access and sharing

Systems and methods for cache optimization

Graphics processing unit processing and caching improvements

Dot product operations on sparse matrix elements

Systolic arithmetic on sparse data

Systems and methods for improving cache efficiency and utilization

Dynamic memory reconfiguration

Sparse optimizations for a matrix accelerator architecture

Computing efficient cross channel operations in parallel computing machines using systolic arrays

Multi-tile memory management

Systolic disaggregation within a matrix accelerator architecture

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Data prefetching for graphics data processing

Asynchronous execution mechanism

Hierarchical general register file (GRF) for execution block

Compute optimization mechanism for deep neural networks

Efficient preemption for graphics processors

Snoop stall reduction on a microprocessor external bus

Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

Scalar core integration

PALANCA SALVADOR

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system