Inventor

LARSON JOHN E

US53 patents

⚠️ This page may combine multiple inventors who share the name “LARSON JOHN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LARSON JOHN E

HEWLETT PACKARD DEVELOPMENT CO

Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency

Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency

Memory module resync

Real-time hardware memory scrubbing

Hot-upgrade/hot-add memory

Hot-replace of memory

Raid memory

Removable memory cartridge system for use with a server or other processor-based device

Techniques for processing out-of-order requests in a processor-based system

Rebuild bus utilization

Hot replace power control sequence logic

Removable memory cartridge system for use with a server or other processor-based device

Error indication in a raid memory system

Error indication in a raid memory system

Hot replace power control sequence logic

Memory module resync

Removable memory cartridge system for use with a server or other processor-based device

Removable memory cartridge system for use with a server or other processor-based device

Method for improving processor performance

Technique for improving processor performance

COMPAQ COMPUTER CORP

System for arbitrating access to memory with dynamic priority assignment

Apparatus and method for entering low power mode in a computer system

System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache

Computer system controller and method with processor write posting hold off on PCI master memory request

System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation

Memory controller having precharge prediction based on processor and PCI bus cycles

System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device

Memory controller having precharge prediction based on processor and PC bus cycles

Memory controller having precharge prediction based on processor and PCI bus cycles

Memory controller including write posting queues, bus read control logic, and a data contents counter

Programmable memory controller having two level look-up for memory timing parameter

Method and apparatus for detecting memory device types

Computer system having a memory controller which performs readahead operations which can be aborted prior to completion

Method of preventing cache corruption during microprocessor pipelined burst operations

(unassigned)

Height adjustable pedestal for chairs and tables

Ergonomic footrests for ergonomic chairs

Height adjustable work chair having a non-swivel seat

Foot rest mechanism for a work chair

Method and apparatus for eliminating the software generated ready-signal to hardware devices that are not part of the memory coherency domain

Gas spring quick release mechanism and method of use

LARSON JOHN E

Workplace chair

User height adjustable tables, support structures, and chairs

Height adjustable work chair

Workplace chair

Wheeled work chair

FREESCALE SEMICONDUCTOR INC

Coherent memory interleaving with uniform latency

Data processing system having a write request network and a write data network

HEWLETT PACKARD COMPANY L P

Memory data verify operation

UNISYS CORP

Dual cache RAM for rapid invalidation

DESHPANDE SANJAY R

Piggy-back snoops for non-coherent memory transactions within distributed processing systems