Inventor

RAMSEY JENS K

US17 patents

⚠️ This page may combine multiple inventors who share the name “RAMSEY JENS K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMSEY JENS K

COMPAQ COMPUTER CORP

Computer system controller and method with processor write posting hold off on PCI master memory request

Synchronizing data between devices

System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation

Cache snoop latency prevention apparatus

Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line

Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus

Multiprocessor cache abitration

Computer system that places a cache memory into low power mode in response to special bus cycles executed on the bus

Memory controller including write posting queues, bus read control logic, and a data contents counter

Microprocessor cache memory way prediction based on the way of previous memory read

Bus arbitration

Single bank, multiple way cache memory

Microprocessor cache memory way prediction based on the way of a previous memory read

Method of preventing cache corruption during microprocessor pipelined burst operations

Computer system cache performance on write allocation cycles by immediately setting the modified bit true

Computer system cache performance on write allocation cycles by immediately setting the modified bit true

HEWLETT PACKARD DEVELOPMENT CO

Technique for improving processor performance