Inventor
CASTAGNETTI RUGGERO
US35 patents
⚠️ This page may combine multiple inventors who share the name “CASTAGNETTI RUGGERO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
28 patentsUS6980462B1Dec 27, 2005
Memory cell architecture for reduced routing congestion
LSI LOGIC CORP58 citations96
US6166403ADec 26, 2000
Integrated circuit having embedded memory with electromagnetic shield
LSI LOGIC CORP72 citations96
US7006370B1Feb 28, 2006
Memory cell architecture
LSI LOGIC CORP50 citations92
US6566171B1May 20, 2003
Fuse construction for integrated circuit structure having low dielectric constant dielectric material
LSI LOGIC CORP30 citations92
US6259146B1Jul 10, 2001
Self-aligned fuse structure and method with heat sink
LSI LOGIC CORP26 citations92
US6218276B1Apr 17, 2001
Silicide encapsulation of polysilicon gate and interconnect
LSI LOGIC CORP28 citations92
US6144076ANov 7, 2000
Well formation For CMOS devices integrated circuit structures
LSI LOGIC CORP51 citations92
US6061264AMay 9, 2000
Self-aligned fuse structure and method with anti-reflective coating
LSI LOGIC CORP18 citations92
US5953614ASep 14, 1999
Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step
LSI LOGIC CORP48 citations92
US6566730B1May 20, 2003
Laser-breakable fuse link with alignment and break point promotion structures
LSI LOGIC CORP15 citations90
US6472715B1Oct 29, 2002
Reduced soft error rate (SER) construction for integrated circuit structures
LSI LOGIC CORP34 citations90
US6778462B1Aug 17, 2004
Metal-programmable single-port SRAM array for dual-port functionality
LSI LOGIC CORP38 citations89
US7082067B2Jul 25, 2006
Circuit for verifying the write speed of SRAM cells
LSI LOGIC CORP17 citations84
US6806551B2Oct 19, 2004
Fuse construction for integrated circuit structure having low dielectric constant dielectric material
LSI LOGIC CORP15 citations84
US6413848B1Jul 2, 2002
Self-aligned fuse structure and method with dual-thickness dielectric
LSI LOGIC CORP14 citations84
US6037233AMar 14, 2000
Metal-encapsulated polysilicon gate and interconnect
LSI LOGIC CORP18 citations84
US6977512B2Dec 20, 2005
Method and apparatus for characterizing shared contacts in high-density SRAM cell design
LSI LOGIC CORP13 citations83
US6664141B1Dec 16, 2003
Method of forming metal fuses in CMOS processes with copper interconnect
LSI LOGIC CORP14 citations82
US6442061B1Aug 27, 2002
Single channel four transistor SRAM
LSI LOGIC CORP15 citations81
US7042747B1May 9, 2006
Ternary CAM bitcells
LSI LOGIC CORP13 citations79
US6066525AMay 23, 2000
Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process
LSI LOGIC CORP15 citations74
US6162714ADec 19, 2000
Method of forming thin polygates for sub quarter micron CMOS process
LSI LOGIC CORP7 citations72
US6828653B1Dec 7, 2004
Method of forming metal fuses in CMOS processes with copper interconnect
LSI LOGIC CORP12 citations71
US6934174B2Aug 23, 2005
Reconfigurable memory arrays
LSI LOGIC CORP5 citations63
US6687114B1Feb 3, 2004
High density memory with storage capacitor
LSI LOGIC CORP4 citations63
US6978407B2Dec 20, 2005
Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory
LSI LOGIC CORP4 citations57
US6586291B1Jul 1, 2003
High density memory with storage capacitor
LSI LOGIC CORP0 citations52
US6770947B2Aug 3, 2004
Laser-breakable fuse link with alignment and break point promotion structures
LSI LOGIC CORP1 citations50