P

Inventor

RAMESH SUBRAMANIAN

US39 patents
⚠️ This page may combine multiple inventors who share the name “RAMESH SUBRAMANIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI LOGIC CORP

17 patents
US8044437B1Oct 25, 2011

Integrated circuit cell architecture configurable for memory or logic elements

LSI LOGIC CORP115 citations98
US6980462B1Dec 27, 2005

Memory cell architecture for reduced routing congestion

LSI LOGIC CORP58 citations96
US6166403ADec 26, 2000

Integrated circuit having embedded memory with electromagnetic shield

LSI LOGIC CORP72 citations96
US7006370B1Feb 28, 2006

Memory cell architecture

LSI LOGIC CORP50 citations92
US6259146B1Jul 10, 2001

Self-aligned fuse structure and method with heat sink

LSI LOGIC CORP26 citations92
US6218276B1Apr 17, 2001

Silicide encapsulation of polysilicon gate and interconnect

LSI LOGIC CORP28 citations92
US6061264AMay 9, 2000

Self-aligned fuse structure and method with anti-reflective coating

LSI LOGIC CORP18 citations92
US5953614ASep 14, 1999

Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step

LSI LOGIC CORP48 citations92
US6778462B1Aug 17, 2004

Metal-programmable single-port SRAM array for dual-port functionality

LSI LOGIC CORP38 citations89
US6413848B1Jul 2, 2002

Self-aligned fuse structure and method with dual-thickness dielectric

LSI LOGIC CORP14 citations84
US6037233AMar 14, 2000

Metal-encapsulated polysilicon gate and interconnect

LSI LOGIC CORP18 citations84
US6977512B2Dec 20, 2005

Method and apparatus for characterizing shared contacts in high-density SRAM cell design

LSI LOGIC CORP13 citations83
US6066525AMay 23, 2000

Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process

LSI LOGIC CORP15 citations74
US6162714ADec 19, 2000

Method of forming thin polygates for sub quarter micron CMOS process

LSI LOGIC CORP7 citations72
US7006369B2Feb 28, 2006

Design and use of a spacer cell to support reconfigurable memories

LSI LOGIC CORP7 citations68
US6934174B2Aug 23, 2005

Reconfigurable memory arrays

LSI LOGIC CORP5 citations63
US6978407B2Dec 20, 2005

Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory

LSI LOGIC CORP4 citations57

DATAGUISE INC

9 patents

HEWLETT PACKARD DEVELOPMENT CO

4 patents

LSI CORP

3 patents

VENKATRAMAN RAMNATH

3 patents

PHILIPS CORP

2 patents

HEWLETT PACKARD CO

1 patent