Inventor
BRACCHITTA JOHN A
US22 patents
Patents
22 patentsUS6483156B1Nov 19, 2002
Double planar gated SOI MOSFET structure
IBM210 citations99
US6882015B2Apr 19, 2005
Intralevel decoupling capacitor, method of manufacture and testing circuit of the same
IBM49 citations96
US6677637B2Jan 13, 2004
Intralevel decoupling capacitor, method of manufacture and testing circuit of the same
IBM66 citations96
US6660596B2Dec 9, 2003
Double planar gated SOI MOSFET structure
IBM46 citations96
US6373095B1Apr 16, 2002
NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area
IBM56 citations96
US6261895B1Jul 17, 2001
Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor
IBM47 citations96
US6130469AOct 10, 2000
Electrically alterable antifuse using FET
IBM70 citations96
US6100123AAug 8, 2000
Pillar CMOS structure
IBM49 citations96
US7195971B2Mar 27, 2007
Method of manufacturing an intralevel decoupling capacitor
IBM26 citations93
US6060358AMay 9, 2000
Damascene NVRAM cell and method of manufacture
IBM30 citations92
US6020777AFeb 1, 2000
Electrically programmable anti-fuse circuit
IBM27 citations92
US6394638B1May 28, 2002
Trench isolation for active areas and first level conductors
IBM19 citations91
US5734192AMar 31, 1998
Trench isolation for active areas and first level conductors
IBM29 citations91
US5518945AMay 21, 1996
Method of making a diffused lightly doped drain device with built in etch stop
IBM37 citations89
US6339015B1Jan 15, 2002
Method of fabricating a non-volatile semiconductor device
IBM7 citations74
US6255699B1Jul 3, 2001
Pillar CMOS structure
IBM10 citations74
US6858889B2Feb 22, 2005
Polysilicon capacitor having large capacitance and low resistance
IBM3 citations63
US6232633B1May 15, 2001
NVRAM cell using sharp tip for tunnel erase
IBM2 citations63
US7323382B2Jan 29, 2008
Intralevel decoupling capacitor, method of manufacture and testing circuit of the same
IBM0 citations52
US6344381B1Feb 5, 2002
Method for forming pillar CMOS
IBM0 citations52
US6420746B1Jul 16, 2002
Three device DRAM cell with integrated capacitor and local interconnect
IBM0 citations51
US6063687AMay 16, 2000
Formation of trench isolation for active areas and first level conductors
IBM0 citations50