Inventor
BALES MARK WILLIAM
US4 patents
Patents
4 patentsUS10339259B2Jul 2, 2019
Method for organizing, controlling, and reporting on design mismatch information in IC physical design data
SYNOPSYS INC0 citations31
US10318685B2Jun 11, 2019
Management of placement constraint regions in an electronic design automation (EDA) system
SYNOPSYS INC0 citations31
US10831964B2Nov 10, 2020
IC physical design using a tiling engine
SYNOPSYS INC0 citations26
US9697313B2Jul 4, 2017
Organization for virtual-flat expansion of physical data in physically-hierarchical IC designs
SYNOPSYS INC0 citations25