Inventor
GUTHRIE GUY LYNN
US215 patents
Patents
50 patentsUS5784576AJul 21, 1998
Method and apparatus for adding and removing components of a data processing system without powering down
IBM197 citations99
US6963967B1Nov 8, 2005
System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture
IBM71 citations98
US6880073B2Apr 12, 2005
Speculative execution of instructions and processes before completion of preceding barrier operations
IBM78 citations98
US6848003B1Jan 25, 2005
Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response
IBM87 citations98
US6748518B1Jun 8, 2004
Multi-level multiprocessor speculation mechanism
IBM142 citations98
US6691220B1Feb 10, 2004
Multiprocessor speculation mechanism via a barrier speculation flag
IBM101 citations98
US6591321B1Jul 8, 2003
Multiprocessor system bus protocol with group addresses, responses, and priorities
IBM89 citations98
US6470427B1Oct 22, 2002
Programmable agent and method for managing prefetch queues
IBM82 citations98
US6405289B1Jun 11, 2002
Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response
IBM148 citations98
US6393528B1May 21, 2002
Optimized cache allocation algorithm for multiple speculative requests
IBM97 citations98
US5898888AApr 27, 1999
Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system
IBM101 citations98
US7073043B2Jul 4, 2006
Multiprocessor system supporting multiple outstanding TLBI operations per partition
IBM67 citations97
US7469318B2Dec 23, 2008
System bus structure for large L2 cache array topology with different latency domains
IBM46 citations96
US6748501B2Jun 8, 2004
Microprocessor reservation mechanism for a hashed address system
IBM59 citations96
US6704843B1Mar 9, 2004
Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange
IBM59 citations96
US6625660B1Sep 23, 2003
Multiprocessor speculation mechanism for efficiently managing multiple barrier operations
IBM74 citations96
US6609192B1Aug 19, 2003
System and method for asynchronously overlapping storage barrier operations with old and new storage operations
IBM70 citations96
US6345342B1Feb 5, 2002
Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line
IBM75 citations96
US6230219B1May 8, 2001
High performance multichannel DMA controller for a PCI host bridge with a built-in cache
IBM44 citations96
US6338119B1Jan 8, 2002
Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance
IBM55 citations95
US7584329B2Sep 1, 2009
Data processing system and method for efficient communication utilizing an Ig coherency state
IBM36 citations93
US7533227B2May 12, 2009
Method for priority scheduling and priority dispatching of store conditional operations in a store queue
IBM29 citations93
US7305523B2Dec 4, 2007
Cache memory direct intervention
IBM38 citations93
US7272664B2Sep 18, 2007
Cross partition sharing of state information
IBM26 citations93
US7228385B2Jun 5, 2007
Processor, data processing system and method for synchronizing access to data in shared memory
IBM39 citations93
US7200717B2Apr 3, 2007
Processor, data processing system and method for synchronizing access to data in shared memory
IBM20 citations93
US7047320B2May 16, 2006
Data processing system providing hardware acceleration of input/output (I/O) communication
IBM40 citations93
US6996679B2Feb 7, 2006
Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members
IBM46 citations93
US6981083B2Dec 27, 2005
Processor virtualization mechanism via an enhanced restoration of hard architected states
IBM32 citations93
US6976148B2Dec 13, 2005
Acceleration of input/output (I/O) communication through improved address translation
IBM23 citations93
US6970976B1Nov 29, 2005
Layered local cache with lower level cache optimizing allocation mechanism
IBM20 citations93
US6910062B2Jun 21, 2005
Method and apparatus for transmitting packets within a symmetric multiprocessor system
IBM19 citations93
US6801984B2Oct 5, 2004
Imprecise snooping based invalidation mechanism
IBM34 citations93
US6785774B2Aug 31, 2004
High performance symmetric multiprocessing systems via super-coherent data mechanisms
IBM44 citations93
US6779086B2Aug 17, 2004
Symmetric multiprocessor systems with an independent super-coherent cache directory
IBM21 citations93
US6763433B1Jul 13, 2004
High performance cache intervention mechanism for symmetric multiprocessor systems
IBM36 citations93
US6763434B2Jul 13, 2004
Data processing system and method for resolving a conflict between requests to modify a shared cache line
IBM22 citations93
US6728873B1Apr 27, 2004
System and method for providing multiprocessor speculation within a speculative branch path
IBM24 citations93
US6725340B1Apr 20, 2004
Mechanism for folding storage barrier operations in a multiprocessor system
IBM31 citations93
US6721856B1Apr 13, 2004
Enhanced cache management mechanism via an intelligent system bus monitor
IBM33 citations93
US6704844B2Mar 9, 2004
Dynamic hardware and software performance optimizations for super-coherent SMP systems
IBM44 citations93
US6658539B2Dec 2, 2003
Super-coherent data mechanisms for shared caches in a multiprocessing system
IBM29 citations93
US6629212B1Sep 30, 2003
High speed lock acquisition mechanism with time parameterized cache coherency states
IBM38 citations93
US6629210B1Sep 30, 2003
Intelligent cache management mechanism via processor access sequence analysis
IBM42 citations93
US6629209B1Sep 30, 2003
Cache coherency protocol permitting sharing of a locked data granule
IBM30 citations93
US6625701B1Sep 23, 2003
Extended cache coherency protocol with a modified store instruction lock release indicator
IBM23 citations93
US6615321B2Sep 2, 2003
Mechanism for collapsing store misses in an SMP computer system
IBM26 citations93
US6606702B1Aug 12, 2003
Multiprocessor speculation mechanism with imprecise recycling of storage operations
IBM45 citations93
US6601144B1Jul 29, 2003
Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis
IBM53 citations93
US6591307B1Jul 8, 2003
Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response
IBM25 citations93
Showing the top 50 of 215 patents by PatentIndex Score.