Inventor
LIU PEICHUN PETER
US34 patents
⚠️ This page may combine multiple inventors who share the name “LIU PEICHUN PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
30 patentsUS5752260AMay 12, 1998
High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses
IBM117 citations98
US6820143B2Nov 16, 2004
On-chip data transfer in multi-processor system
IBM58 citations96
US7043579B2May 9, 2006
Ring-topology based multiprocessor data access bus
IBM40 citations92
US6202128B1Mar 13, 2001
Method and system for pre-fetch cache interrogation using snoop port
IBM24 citations92
US5805855ASep 8, 1998
Data cache array having multiple content addressable fields per cache line
IBM27 citations92
US5787478AJul 28, 1998
Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy
IBM43 citations92
US5699288ADec 16, 1997
Compare circuit for content-addressable memories
IBM59 citations92
US5937429AAug 10, 1999
Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator
IBM20 citations90
US5802567ASep 1, 1998
Mechanism for managing offset and aliasing conditions within a content-addressable memory-based cache memory
IBM30 citations90
US5668972ASep 16, 1997
Method and system for efficient miss sequence cache line allocation utilizing an allocation control cell state to enable a selected match line
IBM47 citations90
US5640534AJun 17, 1997
Method and system for concurrent access in a data cache array utilizing multiple match line selection paths
IBM42 citations90
US7287103B2Oct 23, 2007
Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes
IBM15 citations84
US7055004B2May 30, 2006
Pseudo-LRU for a locking cache
IBM13 citations84
US6510493B1Jan 21, 2003
Method and apparatus for managing cache line replacement within a computer system
IBM18 citations84
US7243200B2Jul 10, 2007
Establishing command order in an out of order DMA command queue
IBM11 citations83
US5761714AJun 2, 1998
Single-cycle multi-accessible interleaved cache
IBM18 citations83
US7069390B2Jun 27, 2006
Implementation of a pseudo-LRU algorithm in a partitioned cache
IBM14 citations82
US7225277B2May 29, 2007
Proxy direct memory access
IBM12 citations81
US6931493B2Aug 16, 2005
Implementation of an LRU and MRU algorithm in a partitioned cache
IBM8 citations74
US6484251B1Nov 19, 2002
Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor
IBM12 citations73
US5905999AMay 18, 1999
Cache sub-array arbitration
IBM13 citations72
US6041390AMar 21, 2000
Token mechanism for cache-line replacement within a cache memory having redundant cache lines
IBM9 citations71
US5890221AMar 30, 1999
Method and system for offset miss sequence handling in a data cache array having multiple content addressable field per cache line utilizing an MRU bit
IBM15 citations71
US7657667B2Feb 2, 2010
Method to provide cache management commands for a DMA controller
IBM5 citations63
US6983387B2Jan 3, 2006
Microprocessor chip simultaneous switching current reduction method and apparatus
IBM6 citations63
US6961820B2Nov 1, 2005
System and method for identifying and accessing streaming data in a locked portion of a cache
IBM4 citations63
US7725618B2May 25, 2010
Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
IBM2 citations62
US6304939B1Oct 16, 2001
Token mechanism for cache-line replacement within a cache memory having redundant cache lines
IBM3 citations60
US7187614B2Mar 6, 2007
Array read access control using MUX select signal gating of the read port
IBM0 citations46
US7231479B2Jun 12, 2007
Round robin selection logic improves area efficiency and circuit speed
IBM0 citations42