Inventor

WALLER WILLIAM K

US52 patents

⚠️ This page may combine multiple inventors who share the name “WALLER WILLIAM K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WALLER WILLIAM K

MICRON TECHNOLOGY INC

Wafer level burn-in of memory integrated circuits

Self-test of a memory device

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for isolating a short-circuited integrated circuit (IC) from other IC&#39;s on a semiconductor wafer

Apparatus and method implementing repairs on a memory device

Device and method for repairing a semiconductor memory

Low-to-high voltage CMOS driver circuit for driving capacitive loads

Multiport RAM based multiprocessor

Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits

Apparatus and method implementing repairs on a memory device

Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for repairing a semiconductor memory

Device and method for repairing a semiconductor memory

Semiconductor memory with local phase generation from global phase signals and local isolation signals

Method and apparatus for detecting intercell defects in a memory device

Semiconductor memory with local phase generation from global phase signals and local isolation signals

System for stressing a memory integrated circuit die

Low-to-high voltage CMOS driver circuit for driving capacitive loads

Method of stress testing memory integrated circuits

Multiport RAM based multiprocessor

Quick response CMOS voltage reference circuit

Compact multifunction logic circuit

Apparatus and method implementing repairs on a memory device

Serial clock noise immunity in a semiconductor memory integrated circuit having a serial port

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for repairing a semiconductor memory

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

System for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Method and apparatus for detecting intercell defects in a memory device

Method for testing a memory device having two or more memory arrays

Device and method for repairing a semiconductor memory

Semiconductor memory with local phase generation from global phase signals and local isolation signals

Memory device having two or more memory arrays and a testpath operably connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath

Low-to-high voltage CMOS driver circuit for driving capacitive loads

Memory device having two or more memory arrays and a testpath connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath

Windowed flash write circuit

Presettable synchronous predecoded counter

Integrated circuit multiport memory having serial access bit mask register and method for writing in the multiport memory

Arithmetic logic unit capable of having a narrow pitch

INTEL CORP

Multi-deck non-volatile memory architecture with improved address line driver circuitry

Method and apparatus to perform a read of a column in a memory accessible by row and/or by column

Technologies for repair of memory with access lines

NAT SEMICONDUCTOR CORP

High speed ECL input buffer for vertical fuse arrays

TEXAS INSTRUMENTS INC

Memory device architecture having global memory array repair capabilities

(unassigned)

Memory wordline decoder having signal-driving amplifier

Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer