Inventor

NEVILL LELAND R

US59 patents

⚠️ This page may combine multiple inventors who share the name “NEVILL LELAND R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NEVILL LELAND R

MICRON TECHNOLOGY INC

Semiconductor chip package

Integrated circuit package including lead frame with electrically isolated alignment feature

Wafer level burn-in of memory integrated circuits

Integrated circuit package alignment feature

Self-test of a memory device

Reduced terminal testing system

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Reduced terminal testing system

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Reduced terminal testing system

Device and method for isolating a short-circuited integrated circuit (IC) from other IC&#39;s on a semiconductor wafer

Reduced terminal testing system

Self-test of a memory device

Reduced terminal testing system

Reduced terminal testing system

Method and apparatus for identifying integrated circuits

Reduced terminal testing system

Circuit and method for enabling a function in a multiple memory device module

Short-resistant decoupling capacitor system for semiconductor circuits

Self-test circuit for memory integrated circuits

Self-test circuit for memory integrated circuits

Data compression circuit and method for testing memory devices

Memory module having on-chip surge capacitors

Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Method of aligning and testing a semiconductor chip package

Uniform temperature environmental testing method for semiconductor devices

System for stressing a memory integrated circuit die

Method of stress testing memory integrated circuits

Burn-in board having discrete test capability

Integrated circuit package alignment feature

Test arrangement for memory devices using a dynamic row for creating test data

Test method and apparatus for writing a memory array with a reduced number of cycles

Tray for processing and/or shipping integrated circuit device

Apparatus and method of controlling the environmental temperature near semiconductor devices under test

Method for processing and/or shipping integrated circuit devices

Integrated circuit module having on-chip surge capacitors

Method and apparatus for determining a set of tests for integrated circuit testing

Integrated circuit module having on-chip surge capacitors

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Data compression circuit and method for testing memory devices

Reduced terminal testing system

Error detection/correction based memory management

Error detection/correction based memory management

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

System for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

(unassigned)

Method and apparatus for back-end repair of multi-chip modules

Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer