Inventor
BINNS FRANK
US24 patents
⚠️ This page may combine multiple inventors who share the name “BINNS FRANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
18 patentsUS6349380B1Feb 19, 2002
Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
INTEL CORP91 citations98
US7158911B2Jan 2, 2007
Methods and apparatus for thermal management of an integrated circuit die
INTEL CORP47 citations96
US6980918B2Dec 27, 2005
Methods and apparatus for thermal management of an integrated circuit die
INTEL CORP41 citations96
US6789037B2Sep 7, 2004
Methods and apparatus for thermal management of an integrated circuit die
INTEL CORP58 citations96
US5724527AMar 3, 1998
Fault-tolerant boot strap mechanism for a multiprocessor system
INTEL CORP160 citations96
US7430578B2Sep 30, 2008
Method and apparatus for performing multiply-add operations on packed byte data
INTEL CORP98 citations95
US6611911B1Aug 26, 2003
Bootstrap processor election mechanism on multiple cluster bus system
INTEL CORP58 citations93
US6925556B2Aug 2, 2005
Method and system to determine the bootstrap processor from a plurality of operable processors
INTEL CORP33 citations91
US8793470B2Jul 29, 2014
Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode
INTEL CORP9 citations83
US6857066B2Feb 15, 2005
Apparatus and method to identify the maximum operating frequency of a processor
INTEL CORP7 citations73
US7966476B2Jun 21, 2011
Determining length of instruction with escape and addressing form bytes without evaluating opcode
INTEL CORP6 citations72
US7917734B2Mar 29, 2011
Determining length of instruction with multiple byte escape code based on information from other than opcode byte
INTEL CORP6 citations72
US9612938B2Apr 4, 2017
Providing status of a processing device with periodic synchronization point in instruction tracing system
INTEL CORP2 citations70
US7783809B2Aug 24, 2010
Virtualization of pin functionality in a point-to-point interface
INTEL CORP2 citations62
US9465647B2Oct 11, 2016
Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM
INTEL CORP2 citations61
US7010678B2Mar 7, 2006
Bootstrap processor election mechanism on multiple cluster bus systems
INTEL CORP4 citations59
US10169268B2Jan 1, 2019
Providing state storage in a processor for system management mode
INTEL CORP0 citations51
US9753832B2Sep 5, 2017
Minimizing bandwith to compress output stream in instruction tracing systems
INTEL CORP1 citations47
COKE JAMES S
2 patentsUS8402252B2Mar 19, 2013
Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode
COKE JAMES S2 citations59
US8161269B2Apr 17, 2012
Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode
COKE JAMES S0 citations48