Inventor

CARPENTER GARY DALE

US46 patents

⚠️ This page may combine multiple inventors who share the name “CARPENTER GARY DALE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CARPENTER GARY DALE

IBM

Reservation management in a non-uniform memory access (NUMA) data processing system

Non-uniform memory access (NUMA) data processing system that permits multiple caches to concurrently hold data in a recent state from which data can be sourced by shared intervention

Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect

Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect

Selective targeting of transactions to devices on a shared bus

Interrupt architecture for a non-uniform memory access (NUMA) data processing system

Level shifter

Interleaved feedforward VCO and PLL

Method and system for avoiding livelocks due to colliding writebacks within a non-uniform memory access system

Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system

Method and system for providing an eviction protocol within a non-uniform memory access system

Method and system for avoiding livelocks due to stale exclusive/modified directory entries within a non-uniform access system

Method and system for avoiding data loss due to cancelled transactions within a non-uniform memory access system

Method and system for arbitrating between bus masters having diverse bus acquisition protocols

Non-uniform memory access (NUMA) data processing system that buffers potential third node transactions to decrease communication latency

Method and system for implementing parity error recovery schemes in a data processing system

Switched management of thermal impedence to reduce temperature excursions

Directory for multi-node coherent bus

Method and apparatus having dynamically scalable clock domains for selectively interconnecting subsystems on a synchronous bus

Non-uniform memory access (NUMA) data processing system that decreases latency by expediting rerun requests

System for recirculation of communication transactions in data processing in the event of communication stall

Queue having distributed multiplexing logic

Method and system for interfacing an upgrade processor to a data processing system

Speech label accelerators and techniques for using same

Power supply interface circuit providing nonvolatile storage with suitable operating and standby voltage levels

Method and apparatus for a scaleable touch panel controller

Skewed inverter delay line for use in measuring critical paths in an integrated circuit

Glitchless wide-range oscillator, and method therefor

Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain using a plurality of storage and multiplexer components

System and method for controlling a multiplexer for selecting between an input clock and an input duty-cycle-corrected clock and outputting the selected clock and an enable signal

Directory for multi-node coherent bus

Method of transparently reducing power consumption of a high-speed communication link

Method of transparently reducing power consumption of a high-speed communication link

ADVANCED RISC MACH LTD

Autonomous verification of circuit design for computing devices

Infrastructure for validating updates via a network of IoT-type devices

Creating and/or enhancing hardware obscurity via randomization points

Systems, devices, and/or processes for behavioral content processing

System-on-a-chip testing for energy harvesting devices

Systems, devices, and/or processes for OMIC and/or behavioral content processing

Autonomous pseudo-random seed generator for computing devices

Method and system for data generation

Logical interleaver

Systems, devices, and/or processes for OMIC content processing and/or communication

Systems, devices, and/or processes for omic content processing and/or partitioning

CARPENTER GARY DALE

Infrastructure for performance based chip-to-chip stacking

Bonding controller guided assessment and optimization for chip-to-chip stacking