Inventor

LEE YU-HUA

TW44 patents

⚠️ This page may combine multiple inventors who share the name “LEE YU-HUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE YU-HUA

TAIWAN SEMICONDUCTOR MFG

Method for forming a fuse in integrated circuit application

Robust dual damascene process

Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings

Process for making embedded DRAM circuits having capacitor under bit-line (CUB)

Modified method for forming cylinder-shaped capacitors for dynamic random access memory (DRAM)

Method to evaluate hemisperical grain (HSG) polysilicon surface

Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cell

Method to form a recess free deep contact

Method to form a protected metal fuse

Keyhole-free process for high aspect ratio gap filing

Method for improving the yield on dynamic random access memory (DRAM) with cylindrical capacitor structures

Etch recipe for embedded DRAM passivation with etch stopping layer scheme

Robust method of forming a cylinder capacitor for DRAM circuits

Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM)

Method for making a fuse structure for improved repaired yields on semiconductor memory devices

Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure

Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits

Method for fabricating a self-aligned contact

Method for making a fuse structure for improved repaired yields on semiconductor memory devices

Method for making cylinder-shaped capacitors for dynamic random access memory

Process to form a crown capacitor structure for a dynamic random access memory cell

Inter-level dielectric planarization approach for a DRAM crown capacitor process

Node process integration technology to improve data retention for logic based embedded dram

Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule

Method for making a more reliable storage capacitor for dynamic random access memory (DRAM)

Adding SF6 gas to improve metal undercut for hardmask metal etching

Method to form capacitance node contacts with improved isolation in a DRAM process

Passivation etching procedure, using a polysilicon stop layer, for repairing embedded DRAM cells

Bond pad scheme for Cu process

Method to define a crown shaped storage node structure, and an underlying conductive plug structure, for a dynamic random access memory cell

Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule

Simple photo development step to form TiSix gate in DRAM process

Process for forming a crown shaped capacitor structure for a DRAM device

Method for forming a cylinder capacitor in the dram process

Laminated silicate glass layer etch stop method for fabricating microelectronic product

Bond pad scheme for Cu process

Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids

Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids

Key-hole free process for high aspect ratio gap filling with reentrant spacer

Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing

Method for manufacturing dual damascene structure with a trench formed first

IND TECH RES INST

Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process

Method of forming a dram cell having a ring-type stacked capacitor

TAIWAN SEMICONDUCTOR FOR MFG C

Borderless dual damascene contact