Inventor

VASHCHENKO VLADISLAV

US150 patents

⚠️ This page may combine multiple inventors who share the name “VASHCHENKO VLADISLAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VASHCHENKO VLADISLAV

NAT SEMICONDUCTOR CORP

Laser powered clock circuit with a substantially reduced clock skew

Low side zener reference voltage extended drain SCR clamps

High voltage ESD LDMOS-SCR with gate reference voltage

Dual direction ESD clamp based on snapback NMOS cell with embedded SCR

BJT with ESD self protection

Substrate independent multiple input bi-directional ESD protection structure

Snapback clamp having low triggering voltage for ESD protection

High voltage tolerant electrostatic discharge (ESD) protection clamp circuitry

Method of forming through-the-wafer metal interconnect structures

Programming method for nonvolatile memory cell

Method of etching a lateral trench under an extrinsic base and improved bipolar transistor

Method of PMOS stacked-gate memory cell programming enhancement utilizing stair-like pulses of control gate voltage

Non-volatile memory cell with gated diode and MOS transistor and method for using such cell

Electrostatic discharge (ESD) protection circuit

LVTSCR with a holding voltage that is greater than a DC bias voltage on a to-be-protected node

MOSFET-based electrostatic discharge (ESD) protection structure with a floating heat sink

Apparatus and method for forming heat sinks on silicon on insulator wafers

Complementary vertical SCRs for SOI and triple well processes

Spin-injection devices on silicon material for conventional BiCMOS technology

Spin-polarization of carriers in semiconductor materials for spin-based microelectronic devices

Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection

Direct implantation of fluorine into the channel region of a PMOS device

Bi-directional ESD protection structure for BiCMOS technology

High holding voltage ESD protection structure for BiCMOS technology

Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage

Avalanche diode with breakdown voltage controlled by gate length

ESD protection bipolar device with internal avalanche diode

Snapback capable NLDMOS, DMOS and extended voltage NMOS devices

Magnetic MEMS switching regulator

ESD protection device with controllable triggering characteristics using driver circuit related to power supply

Method of forming a SiGe DIAC ESD protection structure

Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing such circuit

High holding voltage dual direction ESD clamp

Low reference voltage ESD protection device

ESD protection cell with active pwell resistance control

Self-protecting transistor array

Ultra low leakage MOSFET transistor

Method and structure for addressing hot carrier degradation in high voltage devices

Vertical photodiode with heavily-doped regions of alternating conductivity types

Stacked high-voltage ESD protection clamp with triggering voltage circuit control

High holding voltage ESD protection structure and method

Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal

ESD protection methods and devices using additional terminal in the diode structures

High holding voltage LVTSCR

High-voltage silicon controlled rectifier structure

LVTSCR-like structure with internal emitter injection control

Compact ballasting region design for snapback N-MOS ESD protection structure using multiple local N+ region blocking

VASHCHENKO VLADISLAV

EDS protection diode with pwell-nwell resurf

Low side Zener reference voltage extended drain SCR clamps

EASTMAN KODAK CO

Low-cost method of forming a color imager