Inventor

MIRGORODSKI YURI

US55 patents

⚠️ This page may combine multiple inventors who share the name “MIRGORODSKI YURI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIRGORODSKI YURI

NAT SEMICONDUCTOR CORP

Laser powered clock circuit with a substantially reduced clock skew

BJT with ESD self protection

Snapback clamp having low triggering voltage for ESD protection

Programming method for nonvolatile memory cell

Method of PMOS stacked-gate memory cell programming enhancement utilizing stair-like pulses of control gate voltage

Non-volatile memory cell with gated diode and MOS transistor and method for using such cell

Split gate memory cell with a floating gate in the corner of a trench

Split-gate flash memory cell with a tip in the middle of the floating gate

Split gate memory cell with a floating gate in the corner of a trench

Nonvolatile memory cell

Memory cell with a capacitive structure as a control gate and method of forming the memory cell

Method of forming a region of graded doping concentration in a semiconductor device and related apparatus

Non-volatile memory cell with two capacitors and one PNP transistor and a method of forming such a cell in a 1-poly SOI technology

Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing such circuit

Method and structure for addressing hot carrier degradation in high voltage devices

Programming method for nonvolatile memory cell

Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal

Heating element for enhanced E2PROM

Non-volatile memory cell with poly filled trench as control gate and fully isolated substrate as charge storage

Multistage snapback ESD protection network

Method of forming a vertical MOS transistor

Vertical MOS transistor

Electrostatic discharge (ESD) protection clamp circuitry

Programming method for nonvolatile memory cell

Method of using trenching techniques to make a transistor with a floating gate

Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate current

Method of erasing an NVM cell that utilizes a gated diode

Non-volatile memory (NVM) retention improvement utilizing protective electrical shield

Non-volatile memory structure and erase method with floating gate voltage control

Reducing cross die variability in an EEPROM array

Laser powered integrated circuit

NVM PMOS-cell with one erased and two programmed states

LVTSCR charge pump converter circuit

Retention improvement technique for one time programmable non-volatile memory

Method of forming a split-gate memory cell with a tip in the middle of the floating gate

Non-volatile memory cell with heating element

Method of programming a splity-gate flash memory cell with a positive inhibiting word line voltage

Method of reading an NVM cell that utilizes a gated diode

Fuse-type memory cells based on irreversible snapback device

Mid-size NVM cell and array utilizing gated diode for low current programming

Programmable ESD protection structure

Method of forming non-volatile memory (NVM) retention improvement utilizing protective electrical shield

Method of forming a BJT with ESD self protection

Apparatus and method for storing analog information in EEPROM memory

EASTMAN KODAK CO

Active pixel sensor cell with integrating varactor and method for using such cell

Active pixel sensor cell with integrating varactor and method for using such cell

BABCOCK JEFF A

Method of enhancing charge storage in an E2PROM cell

BABCOCK JEFFREY A

Non-volatile memory cell having a heating element and a substrate-based control gate

FRENCH WILLIAM

Method of forming a region of graded doping concentration in a semiconductor device and related apparatus

MIRGORODSKI YURI

Black box model for large signal transient integrated circuit simulation