Inventor

PATON ERIC N

US57 patents

⚠️ This page may combine multiple inventors who share the name “PATON ERIC N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PATON ERIC N

ADVANCED MICRO DEVICES INC

Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication

Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications

MOSFET having a double gate

Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Method and apparatus for controlling the thickness of a selective epitaxial growth layer

Pre-cleaning for silicidation in an SMOS process

Mosfets incorporating nickel germanosilicided gate and methods for their formation

Process for forming fully silicided gates

Damascene NiSi metal gate high-k transistor

Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Method and apparatus for chemical polishing using field responsive materials

Reducing agent for high-K gate dielectric parasitic interfacial layer

In-situ monitoring during laser thermal annealing

Laser thermal annealing of high-k gate oxide layers

Partial recrystallization of source/drain region before laser thermal annealing

Silicide gate transistors

Method of forming a semiconductor device

Strained silicon MOSFET having reduced leakage and method of its formation

Selective epitaxy to improve silicidation

Strained silicon NMOS having silicon source/drain extensions and method for its fabrication

Post silicide laser thermal annealing to avoid dopant deactivation

Reduced dopant deactivation of source/drain extensions using laser thermal annealing

Nickel alloy for SMOS process silicidation

Laser thermal oxidation to form ultra-thin gate oxide

Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions

Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

Formation of deep amorphous region to separate junction from end-of-range defects

Co-deposition of nitrogen and metal for metal silicide formation

Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient

Methods for post offset spacer clean for improved selective epitaxy silicon growth

Metal silicide gate transistors

Silicide gate transistors

Damascene NiSi metal gate high-k transistor

Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Method of forming a semiconductor device

Fully depleted strained semiconductor on insulator transistor and method of making the same

End-of-range defect minimization in semiconductor device

Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication

Offset spacer process for forming N-type transistors

Polysilicon tilting to prevent geometry effects during laser thermal annealing

Tuning absorption levels during laser thermal annealing

Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Physical vapor deposition of nickel

Scanning laser thermal annealing

Shallow trench isolation process using oxide deposition and anneal

Low-temperature post-dopant activation process

Depletion to avoid cross contamination

Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing

Silicide process using high K-dielectrics

PATON ERIC N

Remote monitoring of critical parameters for calibration of manufacturing equipment and facilities