Inventor
DASTIDAR JAYABRATA GHOSH
US16 patents
⚠️ This page may combine multiple inventors who share the name “DASTIDAR JAYABRATA GHOSH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
13 patentsUS7707472B1Apr 27, 2010
Method and apparatus for routing efficient built-in self test for on-chip circuit blocks
ALTERA CORP23 citations92
US7373621B1May 13, 2008
Constraint-driven test generation for programmable logic device integrated circuits
ALTERA CORP22 citations92
US7111213B1Sep 19, 2006
Failure isolation and repair techniques for integrated circuits
ALTERA CORP38 citations92
US7339816B1Mar 4, 2008
Soft error tolerance for configuration memory in programmable devices
ALTERA CORP10 citations83
US7062685B1Jun 13, 2006
Techniques for providing early failure warning of a programmable circuit
ALTERA CORP14 citations83
US7058534B1Jun 6, 2006
Method and apparatus for application specific test of PLDs
ALTERA CORP13 citations83
US7409669B1Aug 5, 2008
Automatic test configuration generation facilitating repair of programmable circuits
ALTERA CORP9 citations82
US7024327B1Apr 4, 2006
Techniques for automatically generating tests for programmable circuits
ALTERA CORP11 citations82
US8004915B1Aug 23, 2011
Area-efficient memory built-in-self-test circuitry with advanced debug capabilities for distributed memory blocks
ALTERA CORP14 citations81
US7502979B2Mar 10, 2009
Pipelined scan structures for testing embedded cores
ALTERA CORP4 citations62
US7299390B1Nov 20, 2007
Apparatus and method for encrypting security sensitive data
ALTERA CORP4 citations62
US7131043B1Oct 31, 2006
Automatic testing for programmable networks of control signals
ALTERA CORP4 citations62
US7212032B1May 1, 2007
Method and apparatus for monitoring yield of integrated circuits
ALTERA CORP1 citations48
DASTIDAR JAYABRATA GHOSH
3 patentsUS8327199B1Dec 4, 2012
Integrated circuit with configurable test pins
DASTIDAR JAYABRATA GHOSH7 citations77
US8952713B1Feb 10, 2015
Method and apparatus for die testing
DASTIDAR JAYABRATA GHOSH7 citations74
US8259522B1Sep 4, 2012
Area-efficient memory built-in-self-test circuitry with advanced debug capabilities for distributed memory blocks
DASTIDAR JAYABRATA GHOSH4 citations58