Inventor

LAKSHMANAMURTHY SRIDHAR

US52 patents

⚠️ This page may combine multiple inventors who share the name “LAKSHMANAMURTHY SRIDHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAKSHMANAMURTHY SRIDHAR

INTEL CORP

Instruction-assisted cache management for efficient use of cache and memory

Enqueueing entries in a packet queue referencing packets

Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation

Two stage queue arbitration

Apparatus and method for two-stage packet classification using most specific filter matching and transport level sharing

Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces

Methods and apparatus for supporting programmable burst management schemes on pipelined buses

Memory controller module having independent memory controllers for different memory types

Issuing requests to a fabric

Apparatus and method to merge and align data from distributed memory controllers

Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devices

Method and apparatus to communicate flow control information in a duplex network processor system

Scalable, two-stage round robin arbiter with re-circulation and bounded latency

Memory controller with bank sorting and scheduling

Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency

Providing multiple decode options for a system-on-chip (SoC) fabric

Apparatus and method to merge and align data from distributed memory controllers

Method and apparatus to assemble data segments into full packets for efficient packet-based classification

Packet assembly

Method and apparatus for improving network router line rate performance by an improved system for error checking

Ultra low power architecture to support always on path to memory

Providing a sideband message interface for system on a chip (SoC)

Method and apparatus to process switch traffic

Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches

Memory controller for padding and stripping data in response to read and write commands

Method and apparatus to handle parity errors in flow control channels

Network packet buffer allocation optimization in memory bank systems

Network packet buffer allocation optimization in memory bank systems

Method, apparatus and system for handling non-posted memory write transactions in a fabric

Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit

Engine for comparing a key with rules having high and low values defining a range

On-device packet descriptor cache

Sending packets with expanded headers

Supporting multiple channels of a single interface

Providing error handling support to legacy devices

Common idle state, active state and credit management for an interface

Issuing requests to a fabric

Systems and an apparatus with a sideband interface interconnecting agents with at least one router

Aggregating completion messages in a sideband interface

Method, apparatus and system for handling non-posted memory write transactions in a fabric

LAKSHMANAMURTHY SRIDHAR

Providing error handling support to legacy devices

Common idle state, active state and credit management for an interface

Supporting multiple channels of a single interface

Providing multiple decode options for a system-on-chip (SoC) fabric

Sending packets with expanded headers

Issuing requests to a fabric

Aggregating completion messages in a sideband interface

Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache

ADLER ROBERT P

Providing a sideband message interface for system on a chip (SoC)

GOOGLE LLC

Heterogeneous ML accelerator cluster with flexible system resource balance