Inventor

BUSABA FADI Y

US208 patents

⚠️ This page may combine multiple inventors who share the name “BUSABA FADI Y”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BUSABA FADI Y

IBM

Dynamic predictor for coalescing memory transactions

Transaction tracking within a microprocessor

Flushing speculative instruction processing

Prefetching of discontiguous storage locations in anticipation of transactional execution

Dynamic predictor for coalescing memory transactions

Coalescing memory transactions

Method for binary to decimal conversion

Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Prioritization of transactions based on execution by transactional core with super core indicator

Increasing the scope of local purges of structures associated with address translation

Hint instruction for managing transactional aborts in transactional memory computing environments

Address expansion and contraction in a multithreading computer system

Dynamic prediction of hardware transaction resource requirements

Thread context preservation in a multithreading computer system

Multi-granular cache management in multi-processor computing environments

Code optimization to enable and disable coalescing of memory transactions

Salvaging hardware transactions with instructions

Supporting atomic accumulation with an addressable accumulator

Memory access request for a memory protocol

Multithreaded transactions

Multithreaded transactions

Management of shared transactional resources

Dynamic prediction of concurrent hardware transactions resource requirements and allocation

Dynamic enablement of multithreading

Coalescing memory transactions

Alerting hardware transactions that are about to run out of space

Dynamic management of a transaction retry indication

Software indications and hints for coalescing memory transactions

Prefetching of discontiguous storage locations as part of transactional execution

Code optimization to enable and disable coalescing of memory transactions

Salvaging hardware transactions with instructions

Salvaging hardware transactions with instructions

Dispatching multiple threads in a computer

Variable acknowledge rate to reduce bus contention in presence of communication errors

Centralized management of high-contention cache lines in multi-processor computing environments

Multi-pipe dispatch and execution of complex instructions in a superscalar processor

Superscalar microprocessor having multi-pipe dispatch and execution unit

Last iteration loop branch prediction upon counter threshold and resolution upon counter one

Modular binary multiplier for signed and unsigned operands of variable widths

Storage sharing between a secure domain and a non-secure entity

Secure storage query and donation

BUSABA FADI Y

Management of multiple nested transactions

Hardware recovery in multi-threaded processor

Reconfigurable recovery modes in high availability processors

Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors

Variable acknowledge rate to reduce bus contention in presence of communication errors

Method and system for instruction address parity comparison

GLOBALFOUNDRIES INC

Managing high-conflict cache lines in transactional memory computing environments

ALEXANDER KHARY J

Facilitating processing in a computing environment using an extended drain instruction